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LTC2460IDD Datasheet(PDF) 8 Page - Linear Technology |
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LTC2460IDD Datasheet(HTML) 8 Page - Linear Technology |
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8 / 20 page  LTC2460/LTC2462 8 24602f APPLICATIONS INFORMATION mode during the DATA INPUT/OUTPUT state. Once the next conversion is complete, the SLEEP state is entered and power is reduced to less than 2μA. The reference is powered up once CS is brought low. The reference startup time is 12ms (if the reference and compensation capacitor values are both 0.1μF). Upon entering the DATA INPUT/OUTPUT state, SDO outputs the sign (D15) of the conversion result. During this state, the ADC shifts the conversion result serially through the SDO output pin under the control of the SCK input pin. There is no latency in generating this data and the result corresponds to the last completed conversion. A new bit of data appears at the SDO pin following each falling edge detected at the SCK input pin and appears from MSB to LSB. The user can reliably latch this data on every rising edge of the external serial clock signal driving the SCK pin. During the DATA INPUT/OUTPUT state, the LTC2460/ LTC2462 can be programmed to SLEEP or NAP (default) following the next conversion cycle. Data is shifted into the device through the SDI pin on the rising edge of SCK. The input word is 4 bits. If the first bit EN1 = 1 and the second bit EN2 = 0 the device is enabled for programming. The following two bits (SPD and SLP) will be written into the device. SPD (only used for the LTC2460) to select the 60Hz output rate, no offset calibration mode (SPD = 0, default). Set SPD = 1 for 30Hz mode with offset calibration. SPD is ignored for the LTC2462. The next bit (SLP) enables the sleep or nap mode. If SLP = 0 (default) the reference remains powered up at the end of the next conversion cycle. If SLP = 1, the reference powers down following the next conversion cycle. The remaining 12 SDI input bits are ignored (don’t care). SDI may also be tied directly to GND or VDD in order to simplify the user interface. In the case of the LTC2460, the 60Hz output rate is selected if SDI is tied low and the 30Hz output rate is selected if SDI is tied to VDD. The LTC2462 output rate is always 60Hz independent of SDI or SPD. The reference sleep mode is disabled for both the LTC2460 and LTC2462 if SDI is tied to GND or VDD. The DATA INPUT/OUTPUT state concludes in one of two different ways. First, the DATA INPUT/OUTPUT state opera- tion is completed once all 16 data bits have been shifted out and the clock then goes low. This corresponds to the 16th falling edge of SCK. Second, the DATA INPUT/OUT- PUT state can be aborted at any time by a LOW-to-HIGH transition on the CS input. Following either one of these two actions, the LTC2460/LTC2462 will enter the CONVERT state and initiate a new conversion cycle. Power-Up Sequence When the power supply voltage (VCC) applied to the con- verter is below approximately 2.1V, the ADC performs a power-on reset. This feature guarantees the integrity of the conversion result. When VCC rises above this critical threshold, the converter generates an internal power-on reset (POR) signal for approximately 0.5ms. The POR signal clears all internal registers. Following the POR signal, the LTC2460/LTC2462 start a conversion cycle and follow the succession of states shown in Figure 2. The reference startup time following a POR is 12ms (CCOMP = CREFOUT = 0.1μF). The first conver- sion following powerup will be invalid since the reference voltage has not completely settled. The first conversion following power up can be discarded using the data abort command or simply read and ignored. The following con- versions are accurate to the device specifications. Ease of Use The LTC2460/LTC2462 data output has no latency, filter settling delay or redundant results associated with the conversion cycle. There is a one-to-one correspondence between the conversion and the output data. Therefore, Figure 3. Output Code vs VIN+ with VIN– = 0 (LTC2462) VIN +/VREF+ –0.001 4 12 20 0.001 24602 F03 –4 –12 0 8 16 –8 –16 –20 –0.005 0 0.005 0.0015 SIGNALS BELOW GND |
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