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M48Z02-200PC1 Datasheet(PDF) 7 Page - STMicroelectronics |
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M48Z02-200PC1 Datasheet(HTML) 7 Page - STMicroelectronics |
7 / 21 page M48Z02, M48Z12 Operation modes Doc ID 2420 Rev 7 7/21 2 Operation modes The M48Z02/12 also has its own power-fail detect circuit. The control circuitry constantly monitors the single 5 V supply for an out of tolerance condition. When VCC is out of tolerance, the circuit write protects the SRAM, providing a high degree of data security in the midst of unpredictable system operation brought on by low VCC. As VCC falls below approximately 3 V, the control circuitry connects the battery which maintains data operation until valid power returns. Table 2. Operating modes Note: X = VIH or VIL; VSO = battery backup switchover voltage. 2.1 Read mode The M48Z02/12 is in the READ mode whenever W (WRITE enable) is high and E (chip enable) is low. The device architecture allows ripple-through access of data from eight of 16,384 locations in the static storage array. Thus, the unique address specified by the 11 Address Inputs defines which one of the 2,048 bytes of data is to be accessed. Valid data will be available at the data I/O pins within address access time (tAVQV) after the last address input signal is stable, providing that the E and G access times are also satisfied. If the E and G access times are not met, valid data will be available after the latter of the chip enable access time (tELQV) or output enable access time (tGLQV). The state of the eight three-state data I/O signals is controlled by E and G. If the outputs are activated before tAVQV, the data lines will be driven to an indeterminate state until tAVQV. If the address inputs are changed while E and G remain active, output data will remain valid for output data hold time (tAXQX) but will go indeterminate until the next address access. Mode VCC E G W DQ0- DQ7 Power Deselect 4.75 to 5.5 V or 4.5 to 5.5 V VIH X X High Z Standby WRITE VIL XVIL DIN Active READ VIL VIL VIH DOUT Active READ VIL VIH VIH High Z Active Deselect VSO to VPFD(min) (1) 1. See Table 10 on page 16 for details. X X X High Z CMOS standby Deselect ≤ VSO(1) X X X High Z Battery backup mode |
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