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IC-TW2QFN24 Datasheet(PDF) 6 Page - IC-Haus GmbH |
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IC-TW2QFN24 Datasheet(HTML) 6 Page - IC-Haus GmbH |
6 / 30 page iC-TW2 8-BIT SIN/COS INTERPOLATION IC WITH INTEGRATED EEPROM Rev D3, Page 6/30 ELECTRICAL CHARACTERISTICS Operating conditions: VDD = VDDA = 3.0...5.5 V, Tj = -40...125 °C, unless otherwise stated Item Symbol Parameter Conditions Unit No. Min. Typ. Max. Digital Inputs CLKSEL, CLKEXT 601 Vt()hi Input Threshold Voltage hi VDD = 3.3 V +/- 10 % 1.5 V VDD = 5.0 V +/- 10 % 3.3 V 602 Vt()lo Input Threshold Voltage lo VDD = 3.3 V +/- 10 % 0.8 V VDD = 5.0 V +/- 10 % 1.0 V 603 Ipd() Input Pull-down Current V() = 1 V...VDD 4 µA 604 Vpd() Input Pull-down Voltage I() = 3 µA 500 mV Digital Outputs A_U, NA_NU, B_V, NB_NV, Z_W, NZ_NW 701 Vs()hi Output Saturation Voltage hi Vs()hi = V(VDD) - V(), I() = -6 mA; VDD = 3.3 V +/- 10 % 0.5 V VDD = 5.0 V +/- 10 % 0.4 V 702 Isc()hi Short-circuit Current hi V() = GND -100 -15 mA 703 Vs()lo Output Saturation Voltage lo I() = 6 mA; VDD = 3.3 V +/- 10 % 0.3 V VDD = 5.0 V +/- 10 % 0.25 V 704 Isc()lo Short-circuit Current lo V() = VDD 20 140 mA 705 tr() Output Rise time VDD = 3.0 V, CL() = 10 pF 4 ns 706 tf() Output Fall Time VDD = 3.0 V, CL() = 10 pF 4 ns 707 I()max Permissible Load Current source and sink -10 10 mA 708 twhi Duty Cycle at Output A, B referred to period T, see Fig. 1 50 % 709 tAB Output Phase A vs. B referred to period T, see Fig. 1 25 % 710 tMTD Minimum Transition Distance see Fig. 1 1/ fcore Signal Processing 801 AAabs Absolute Angular Accuracy referred to 360° input signal -6 6 DEG GC(2:0) = 1 INTER(7:0) = 0 FREQ(6:0) = 127 f() < 50 Hz 802 AArel Relative Angular Accuracy referred to period of A, B -20 20 % GC(2:0) = 1 INTER(7:0) = 0 FREQ(6:0) = 127 f() < 50 Hz 803 ABrel Relative Angular Accuracy A vs. B 1/2 AArel % Index Comparator PINZ, NINZ 901 Vin()sig Permissible Input Voltage Range 0.0 VDD V 902 Vin()os Input Referred Offset Voltage -15 +15 mV 903 Vin()step Comparator Offset Step Size OFSZ = 0..7 1.5 mV OFSZ = 8..15 -1.5 mV Power-Down-Reset A01 VDDon Turn-on Threshold VDD (power on release) 1.8 V A02 tbusy()cfg Duration of Startup Configuration 20 ms |
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