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FX802 Datasheet(PDF) 6 Page - CML Microcircuits |
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FX802 Datasheet(HTML) 6 Page - CML Microcircuits |
6 / 14 page 6 Store and Play Speech Speech Store Commands 62 H STORE ‘N’ PAGES – START PAGE ‘X’ (immediate). 63 H STORE ‘N’ PAGES – START PAGE ‘X’ (buffered). The digitised speech from the Delta Encoder is stored in consecutive DRAM locations with the Speech Store Counters sequencing through the DRAM addresses and counting the number of complete ‘pages’ stored since the start of execution of the command. As soon as the command has terminated the following events take place: (1) The “Store Command Complete” bit in the Status Register (Table 6) is set. (2) An “Interrupt Request” (IRQ) is sent (if enabled) to the µC. (3) The next Speech Store command (if present) is immediately taken from the Store Command Buffer and execution of the new command commences. Speech Playback is controlled by similar commands: 64 H PLAY ‘N’ PAGES – START PAGE ‘X’ (immediate). 65 H PLAY ‘N’ PAGES – START PAGE ‘X’ (buffered). using the Speech Play Counters and Play Command Buffer. As soon as the Play Command has completed, the “Play Command Complete” bit in the Status Register is set and an Interrupt Request generated (if enabled). If no 'next' command is waiting in the Play Command Buffer when a speech Play command finishes, a continuous idle code (0101.....0101) will be fed to the Delta Decoder. Speech “data” is stored or recovered at the selected Encode or Decode sample rate (Table 3). Store or Play Command Complete bits in the Status Register are cleared by the next Store or Play command received from the µC, or by a General Reset command. The IRQ output is cleared by reading the Status Register. 61 H READ STATUS REGISTER (Table 6). To provide continuity of speech commands, both Store and Play commands can be presented to the FX802 in one of two formats; Immediate or Buffered. An Immediate command will be started on completion of its loading, irrespective of the condition of the current command. A Buffered command will be acted upon on the completion of the current Store or Play command, unless Speech Synchronization Bits (Control Register) are set. Buffering of commands lets the DVSR Codec execute a series of commands without intervening gaps, even though the µController may take several milliseconds to respond to each “Command Complete” Interrupt Request. In either case, the Store or Play Command Complete bit of the Status Register will be cleared. Store/Play Speech Synchronization – (Table 4) This facility is provided, primarily, for Time Domain Scrambling applications. Speech Synchronization bits in the Control Register will produce the effects described below: No Speech Sync Set; Store and Play operations may take place completely independently. Store after Play; The next “buffered” Store command will start on completion of a Play operation, whilst the next Play command (if any) sequence continues normally. Play after Store; The next “buffered” Play command will start on completion of a Store operation, whilst the next Store command (if any) sequence continues normally. These actions will continue whilst ‘Speech Sync’ bits remain set. Controlling Protocol ...... DRAM Available “Speech Nominal Sample Rates (kbits/s) Size Bits Pages” 16 25 32 50 64 256kbits 262144 256 16.0 10.0 8.0 5.0 4.0 1024k 1048576 1024 65.0 42.0 32.0 20.0 16.0 2Mbits 2097152 2048 131.0 84.0 65.0 42.0 32.0 3M 3145728 3072 196.0 126.0 98.0 63.0 49.0 4M 4194304 4096 262.0 168.0 131.0 84.0 65.5 Store and Play Times (seconds) Table 2 Sampling Clock Rates vs Speech Storage/Playback Times DRAM Speech Capacity 28-pin/lead versions of the FX802 may be used with a single 256kbit DRAM or with up to 4 x 1Mbit DRAM. 24-pin/lead versions may only be used with a single 256kbit or 1Mbit DRAM. The different Encode and Decode sampling clock rates available enable the user to set voice store and play times against recovered speech quality. Table 2 gives information on storage capacity and Store/Playback times. Speech data can be replayed at a different sample rate or in a reverse sequence, see Control Register for details. |
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