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ISO7420FE Datasheet(PDF) 2 Page - Texas Instruments |
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ISO7420FE Datasheet(HTML) 2 Page - Texas Instruments |
2 / 19 page ISO7420E, ISO7420FE ISO7421E, ISO7421FE SLLSE45B – DECEMBER 2010 – REVISED JANUARY 2011 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. PIN DESCRIPTIONS PIN I/O DESCRIPTION NAME ISO7420x ISO7421x INA 2 7 I Input, channel A INB 3 3 I Input, channel B GND1 4 4 – Ground connection for VCC1 GND2 5 5 – Ground connection for VCC2 OUTA 7 2 O Output, channel A OUTB 6 6 O Output, channel B VCC1 1 1 – Power supply, VCC1 VCC2 8 8 – Power supply, VCC2 Table 1. FUNCTION TABLE(1) OUTPUT INPUT OUTPUT OUTA, OUTB INPUT SIDE SIDE INA, INB ISO7420E / ISO7420FE / VCC VCC ISO7421E ISO7421FE H H H PU PU L L L Open H(2) L(3) PD PU X H(2) L(3) PU PD X Z Z (1) PU = Powered up (VCC ≥ 3 V); PD = Powered down (VCC ≤ 2.4 V); X = Irrelevant; H = High level; L = Low level; Z = High Impedance (2) In fail-safe condition, output defaults to high level (3) In fail-safe condition, output defaults to low level AVAILABLE OPTIONS RATED INPUT CHANNEL MARKED ORDERING PRODUCT PACKAGE RATED TA ISOLATION THRESHOLD DIRECTION AS NUMBER ISO7420ED (rail) ISO7420E(1) SO7420 ISO7420EDR (reel) Same ISO7420FED (rail) ISO7420FE I7420F ~1.5 V TTL ISO7420FEDR (reel) 2.5 KVRMS D-8 (CMOS –40°C to 125°C ISO7421ED (rail) compatible) ISO7421E(1) SO7421 ISO7421EDR (reel) Opposite ISO7421FED (rail) ISO7421FE(1) I7421F ISO7421FEDR (reel) (1) Product Preview 2 Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ISO7420E, ISO7420FE ISO7421E, ISO7421FE |
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