Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.NET

X  

ADSP-BF561SKBCZ-6A Datasheet(PDF) 3 Page - Analog Devices

Part # ADSP-BF561SKBCZ-6A
Description  Blackfin Embedded Symmetric Multiprocessor
Download  64 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADSP-BF561SKBCZ-6A Datasheet(HTML) 3 Page - Analog Devices

  ADSP-BF561SKBCZ-6A Datasheet HTML 1Page - Analog Devices ADSP-BF561SKBCZ-6A Datasheet HTML 2Page - Analog Devices ADSP-BF561SKBCZ-6A Datasheet HTML 3Page - Analog Devices ADSP-BF561SKBCZ-6A Datasheet HTML 4Page - Analog Devices ADSP-BF561SKBCZ-6A Datasheet HTML 5Page - Analog Devices ADSP-BF561SKBCZ-6A Datasheet HTML 6Page - Analog Devices ADSP-BF561SKBCZ-6A Datasheet HTML 7Page - Analog Devices ADSP-BF561SKBCZ-6A Datasheet HTML 8Page - Analog Devices ADSP-BF561SKBCZ-6A Datasheet HTML 9Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 3 / 64 page
background image
ADSP-BF561
GENERAL DESCRIPTION
The ADSP-BF561 processor is a high performance member of
the Blackfin
® family of products targeting a variety of multime­
dia, industrial, and telecommunications applications. At the
heart of this device are two independent Analog Devices
Blackfin processors. These Blackfin processors combine a dual-
MAC state-of-the-art signal processing engine, the advantage of
a clean, orthogonal RISC-like microprocessor instruction set,
and single instruction, multiple data (SIMD) multimedia capa­
bilities in a single instruction set architecture.
The ADSP-BF561 processor has 328K bytes of on-chip memory.
Each Blackfin core includes:
• 16K bytes of instruction SRAM/cache
• 16K bytes of instruction SRAM
• 32K bytes of data SRAM/cache
• 32K bytes of data SRAM
• 4K bytes of scratchpad SRAM
Additional on-chip memory peripherals include:
• 128K bytes of low latency on-chip L2 SRAM
• Four-channel internal memory DMA controller
• External memory controller with glueless support for
SDRAM, mobile SDRAM, SRAM, and flash.
PORTABLE LOW POWER ARCHITECTURE
Blackfin processors provide world-class power management
and performance. Blackfin processors are designed in a low
power and low voltage design methodology and feature
dynamic power management, the ability to vary both the voltage
and frequency of operation to significantly lower overall power
consumption. Varying the voltage and frequency can result in a
substantial reduction in power consumption, compared with
just varying the frequency of operation. This translates into
longer battery life for portable appliances.
BLACKFIN PROCESSOR CORE
As shown in Figure 2, each Blackfin core contains two multi­
plier/accumulators (MACs), two 40-bit ALUs, four video ALUs,
and a single shifter. The computational units process 8-bit,
16-bit, or 32-bit data from the register file.
Each MAC performs a 16-bit by 16-bit multiply in every cycle,
with accumulation to a 40-bit result, providing eight bits of
extended precision. The ALUs perform a standard set of arith­
metic and logical operations. With two ALUs capable of
operating on 16-bit or 32-bit data, the flexibility of the computa­
tion units covers the signal processing requirements of a varied
set of application needs.
Each of the two 32-bit input registers can be regarded as two
16-bit halves, so each ALU can accomplish very flexible single
16-bit arithmetic operations. By viewing the registers as pairs of
16-bit operands, dual 16-bit or single 32-bit operations can be
accomplished in a single cycle. By further taking advantage of
the second ALU, quad 16-bit operations can be accomplished
simply, accelerating the per cycle throughput.
The powerful 40-bit shifter has extensive capabilities for per­
forming shifting, rotating, normalization, extraction, and
depositing of data. The data for the computational units is
found in a multiported register file of sixteen 16-bit entries or
eight 32-bit entries.
A powerful program sequencer controls the flow of instruction
execution, including instruction alignment and decoding. The
sequencer supports conditional jumps and subroutine calls, as
well as zero overhead looping. A loop buffer stores instructions
locally, eliminating instruction memory accesses for tight
looped code.
Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches from memory. The DAGs
share a register file containing four sets of 32-bit Index, Modify,
Length, and Base registers. Eight additional 32-bit registers
provide pointers for general indexing of variables and stack
locations.
Blackfin processors support a modified Harvard architecture in
combination with a hierarchical memory structure. Level 1 (L1)
memories are those that typically operate at the full processor
speed with little or no latency. Level 2 (L2) memories are other
memories, on-chip or off-chip, that may take multiple processor
cycles to access. At the L1 level, the instruction memory holds
instructions only. The two data memories hold data, and a dedi­
cated scratchpad data memory stores stack and local variable
information. At the L2 level, there is a single unified memory
space, holding both instructions and data.
In addition, half of L1 instruction memory and half of L1 data
memory may be configured as either Static RAMs (SRAMs) or
caches. The Memory Management Unit (MMU) provides mem­
ory protection for individual tasks that may be operating on the
core and may protect system registers from unintended access.
The architecture provides three modes of operation: user mode,
supervisor mode, and emulation mode. User mode has
restricted access to certain system resources, thus providing a
protected software environment, while supervisor mode has
unrestricted access to the system and core resources.
The Blackfin instruction set has been optimized so that 16-bit
op-codes represent the most frequently used instructions,
resulting in excellent compiled code density. Complex DSP
instructions are encoded into 32-bit op-codes, representing fully
featured multifunction instructions. Blackfin processors sup­
port a limited multi-issue capability, where a 32-bit instruction
can be issued in parallel with two 16-bit instructions, allowing
the programmer to use many of the core resources in a single
instruction cycle.
The Blackfin assembly language uses an algebraic syntax for
ease of coding and readability. The architecture has been opti­
mized for use in conjunction with the VisualDSP C/C++
compiler, resulting in fast and efficient software
implementations.
Rev. E
|
Page 3 of 64
|
September 2009


Similar Part No. - ADSP-BF561SKBCZ-6A

ManufacturerPart #DatasheetDescription
logo
Analog Devices
ADSP-BF561SKBCZ-6A2 AD-ADSP-BF561SKBCZ-6A2 Datasheet
3Mb / 64P
   Blackfin짰 Embedded Symmetric Multiprocessor
REV. B
More results

Similar Description - ADSP-BF561SKBCZ-6A

ManufacturerPart #DatasheetDescription
logo
Analog Devices
ADSP-BF561 AD-ADSP-BF561_06 Datasheet
2Mb / 60P
   Blackfin Embedded Symmetric Multiprocessor
REV. A
ADSP-BF561 AD-ADSP-BF561_07 Datasheet
3Mb / 64P
   Blackfin짰 Embedded Symmetric Multiprocessor
REV. B
ADSP-BF561 AD-ADSP-BF561 Datasheet
508Kb / 52P
   Blackfin Embedded Symmetric Multi-Processor
REV. C
ADSP-BF533SBBC-500 AD-ADSP-BF533SBBC-500 Datasheet
2Mb / 64P
   Blackfin Embedded Processor
Rev. I
ADSP-BF531 AD-ADSP-BF531 Datasheet
671Kb / 56P
   Blackfin Embedded Processor
REV. 0
ADSP-BF538 AD-ADSP-BF538 Datasheet
3Mb / 56P
   Blackfin Embedded Processor
Rev. PrD
ADSP-BF538 AD-ADSP-BF538_15 Datasheet
3Mb / 60P
   Blackfin Embedded Processor
Rev. E
ADSP-BF538F AD-ADSP-BF538F_15 Datasheet
3Mb / 60P
   Blackfin Embedded Processor
Rev. E
ADSP-BF527 AD-ADSP-BF527_15 Datasheet
2Mb / 88P
   Blackfin Embedded Processor
REV. D
ADSP-BF544 AD-ADSP-BF544_15 Datasheet
3Mb / 102P
   Blackfin Embedded Processor
Rev. E
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.NET
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com