FMP3216DAX datasheet(4/11 Pages) FIDELIX

Part #	FMP3216DAX

Description	2M x 16 bit Super Low Power and Low Voltage Full CMOS RAM

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Manufacturer	FIDELIX [FIDELIX]

Direct Link	http://www.fidelix.co.kr

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FMP3216DAx

CMOS LPRAM

CAPACITANCE1) (f=1MHz , TA=25’C)

It

Sb l

Tt C

diti

Mi

M

Uit

DC AND OPERATING CHARACTERISTICS

1. Capacitance is sampled, not 100% tested.

Item

Symbol

Test Condition

Min

Max

Unit

Input capacitance

CIN

VIN=0V

-

8

pF

Input/Output capacitance

CIO

VIO=0V

-

8

pF

Item

Symbol

Test Conditions

Min

Max

Unit

Input leakage current

ILI

VIN=VSS to VCC

-1

1

uA

Input leakage current

ILI

VIN VSS to VCC

1

uA

Output leakage current

ILO

/CS=VIH, /ZZ=VIH, /OE=VIH or /WE=VIL, VIO=VSS to VCC

-1

1

uA

Average operating current

ICC1

Cycle time=1us, 100%duty, IIO=0mA, /CS≤0.2V, /ZZ=VIH,

VIN≤0.2V or VIN≥VCC-0.2V

-3

mA

ICC2

Cycle time=Min, IIO=0mA, 100% duty, /CS=VIL, /ZZ=VIH,

VIN=VIL or VIH

-20

mA

Output low voltage

VOL

IOL=0.5mA

0.2VCCQ

V

Output high voltage

VOH

IOH=-0.5mA

0.8VCCQ

V

St db C

t(TTL)

ISB

/CS VIH /ZZ VIH Oth

i

t VIH

VIL

03

A

Standby Current(TTL)

ISB

/CS=VIH, /ZZ=VIH, Other inputs=VIH or VIL

-

0.3

mA

Standby Current(CMOS)

ISB1

/CS≥VCC-0.2V, /ZZ≥VCC-0.2V, Other inputs=0~VCC

-

120

uA

Low Power Modes

ISB0

/ZZ≤0.2V, Other inputs=0~VCC, No refresh(DPD)

-

10

uA

ISB0a

/ZZ≤0.2V, Other inputs=0~VCC, ¼ refresh area selection

-

90

uA

ISB0b

/ZZ≤0.2V, Other inputs=0~VCC, ½ refresh area selection

-

100

uA

ISB0c

/ZZ≤0.2V, Other inputs=0~VCC, All refresh area selection

-

120

uA

Operating Range

Device

Range

Ambient Temperature

VCC

VCCQ

FMP3216DAx-XxxS

Special

-10℃ to +60℃

2.7V to 3.3V

2.7V to VCC

FMP3216DAx-XxxC

Commercial

0℃ to +70℃

FMP3216DAx-XxxE

Extended

-25℃ to +85℃

FMP3216DAx-XxxI

Industrial

-40℃ to +85℃

Operating Range

AC Input/Output Reference Waveform

NOTE:

1. AC test inputs are driven at VCCQ for a logic 1 and VSS for a logic 0. Input rise and fall times (10% to 90%) < 1.6ns.

2 Inp t timing begins at VCCQ/2

Test Points

VCCQ/23

VCCQ/2 2

VCCQ

VSS

Input1

Output

2. Input timing begins at VCCQ/2.

3. Output timing ends at VCCQ/2.

AC Output Load Circuit

DUT

50

&

Test Point

VCCQ/2

Revision 0.1

Jul. 2010

4

30pF

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