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TJA1028 Datasheet(PDF) 4 Page - NXP Semiconductors |
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TJA1028 Datasheet(HTML) 4 Page - NXP Semiconductors |
4 / 24 page TJA1028 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 25 February 2011 4 of 24 NXP Semiconductors TJA1028 LIN transceiver with integrated voltage regulator 6. Pinning information 6.1 Pinning 6.2 Pin description [1] HVSON8 package die supply ground is connected to both the GND pin and the exposed center pad. The GND pin must be soldered to board ground. For enhanced thermal and electrical performance, it is recommended that the exposed center pad also be soldered to board ground. 7. Functional description The TJA1028 combines the functionality of a LIN transceiver and a voltage regulator in a single chip and offers wake-up by bus activity. The voltage regulator is designed to power the Electronic Control Unit’s (ECU) microcontroller and its peripherals. The TJA1028 is the interface between a LIN master/slave protocol controller and the physical bus in a Local Interconnect Network (LIN). It is LIN 2.0/2.1/SAE J2602 compliant and achieves optimum ElectroMagnetic Compatibility (EMC) performance by wave shaping the LIN output. a. TJA1028T/xxx/xx: SO8 b. TJA1028TK/xxx/xx: HVSON8 Fig 2. Pin configuration diagrams TJA1028T VBAT VCC EN GND TXD LIN RXD 015aaa082 1 2 3 4 6 5 8 7 RSTN 015aaa244 TJA1028TK RXD GND LIN TXD EN RSTN VBAT VCC Transparent top view 4 5 3 6 2 7 1 8 terminal 1 index area Table 3. Pin description Symbol Pin Description VBAT 1 battery supply for the TJA1028 EN 2 enable input GND 3[1] ground LIN 4 LIN bus line RXD 5 LIN receive data output TXD 6 LIN transmit data input RSTN 7 reset output (active LOW) VCC 8 voltage regulator output |
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