Electronic Components Datasheet Search |
|
SY100S834LZCTR Datasheet(PDF) 1 Page - Micrel Semiconductor |
|
SY100S834LZCTR Datasheet(HTML) 1 Page - Micrel Semiconductor |
1 / 6 page 1 Precision Edge® SY100S834 SY100S834L Micrel, Inc. M9999-111009 hbwhelp@micrel.com or (408) 955-1690 The SY100S834/L is low skew (÷1, ÷2, ÷4) or (÷2, ÷4, ÷8) clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The devices can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. In addition, by using the VBB output, a sinusoidal source can be AC-coupled into the device. If a single-ended input is to be used, the VBB output should be connected to the CLK input and bypassed to ground via a 0.01µF capacitor. The VBB output is designed to act as the switching reference for the input of the SY100S834/L under single-ended input conditions. As a result, this pin can only source/sink up to 0.5mA of current. The Function Select (FSEL) input is used to determine what clock generation chip function is. When FSEL input is LOW, SY100S834/L functions as a divide by 2, by 4 and by 8 clock generation chip. However, if FSEL input is HIGH, it functions as a divide by 1, by 2 and by 4 clock generation chip. This latter feature will increase the clock frequency by two folds. The common enable (EN) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. An internal runt pulse could lead to losing synchronization between the internal divider stages. The internal enable flip-flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input. Upon start-up, the internal flip-flops will attain a random state; the master reset (MR) input allows for the synchronization of the internal dividers, as well as for multiple SY100S834/Ls in a system. DESCRIPTION ■ 3.3V (SY100S834L) and 5V (SY100S834) power supply options ■ 50ps output-to-output skew ■ Synchronous enable/disable ■ Master Reset for synchronization ■ Internal 75KΩ input pull-down resistors ■ Available in 16-pin SOIC package FEATURES Rev.: I Amendment: /0 Issue Date: November 2009 ( ÷1, ÷2, ÷4) OR (÷2, ÷4, ÷8) CLOCK GENERATION CHIP Precision Edge® SY100S834 SY100S834L Pin Function CLK Differential Clock Inputs FSEL Function Select EN Synchronous Enable MR Master Reset VBB Reference Output Q0 Differential ÷1 or ÷2 Outputs Q1 Differential ÷2 or ÷4 Outputs Q2 Differential ÷4 or ÷8 Outputs PIN NAMES CLK EN MR Function ZL L Divide ZZ H L Hold Q0–2 XX H Reset Q0–2 Notes: Z = LOW-to-HIGH transition ZZ = HIGH-to-LOW transition TRUTH TABLE FSEL Q0 Outputs Q1 Outputs Q2 Outputs L Divide by 2 Divide by 4 Divide by 8 H Divide by 1 Divide by 2 Divide by 4 Precision Edge is a registered trademark of Micrel, Inc. Precision Edge® |
Similar Part No. - SY100S834LZCTR |
|
Similar Description - SY100S834LZCTR |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |