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SY87701VZH Datasheet(PDF) 5 Page - Micrel Semiconductor |
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SY87701VZH Datasheet(HTML) 5 Page - Micrel Semiconductor |
5 / 15 page SY87701V 5 Micrel, Inc. M9999-073008 hbwhelp@micrel.com or (408) 955-1690 CHARACTERISTICS Performance The SY87701V PLL complies with the jitter specifications proposed for SONET/SDH equipment defined by the Bellcore Specifications: GR-253-CORE, Issue 2, December 1995 and ITU-T Recommendations: G.958 document, when used with differential inputs and outputs. Input Jitter Tolerance Input jitter tolerance is defined as the peak-to-peak amplitude of sinusoidal jitter applied on the input signal that causes an equivalent 1dB optical/electrical power penalty. SONET input jitter tolerance requirement condition is the input jitter amplitude which causes an equivalent of 1dB power penalty. Figure 1. Input Jitter Tolerance OC/STS-N f0 f1 f2 f3 ft Level (Hz) (Hz) (Hz) (kHz) (kHz) 3 10 30 300 6.5 65 12 10 30 300 25 250 15 1.5 0.40 f0 f1 f2 f4 ft Frequency -20dB/decade -20dB/decade A Figure 2. Jitter Transfer OC/STS-N fc P Level (kHz) (dB) 3 130 0.1 12 225 0.1 0.1 -20 fc Jitter Transfer (dB) Frequency -20dB/decade Acceptable Range Jitter Transfer Jitter transfer function is defined as the ratio of jitter on the output OC-N/STS-N signal to the jitter applied on the input OC-N/STS-N signal versus frequency. Jitter transfer requirements are shown in Figure 2. Jitter Generation The jitter of the serial clock and serial data outputs shall not exceed .01 U.I. rms when a serial data input with no jitter is presented to the serial data inputs. |
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