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SY89426JYTR Datasheet(PDF) 2 Page - Micrel Semiconductor |
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SY89426JYTR Datasheet(HTML) 2 Page - Micrel Semiconductor |
2 / 7 page 2 Precision Edge® SY89426 Micrel, Inc. M9999-112105 hbwhelp@micrel.com or (408) 955-1690 PACKAGE/ORDERING INFORMATION 28-Pin PLCC (J28-1) Ordering Information(1) Package Operating Package Lead Part Number Type Range Marking Finish SY89426JC J28-1 Commercial SY89426JC Sn-Pb SY89426JCTR(2) J28-1 Commercial SY89426JC Sn-Pb SY89426JY(3) J28-1 Industrial SY89426JY with Matte-Sn Pb-Free bar line indicator Pb-Free SY89426JYTR(2, 3) J28-1 Industrial SY89426JY with Matte-Sn Pb-Free bar line indicator Pb-Free Notes: 1. Contact factory for die availability. Dice are guaranteed at T A = 25°C, DC Electricals only. 2. Tape and Reel. 3. Pb-Free package is recommended for new designs. 26 27 28 1 2 3 4 18 17 16 15 14 13 12 25 24 23 22 21 20 19 56 7 8 9 10 11 GND VCC PLCC TOP VIEW J28-1 VCC CK622P CK622N VCCO CK155 GND GND SEL39 RFCK VCC NC SEL78 INPUTS RFCK [Reference Clock] TTL Reference clock IN. (38.88, 51.84 or 77.76MHz). SEL39 [38.88MHz Select] TTL Logic HIGH on this pin denotes a 38.88MHz input reference clock. Tie to logic LOW if input is not 38.88MHz. SEL78 [77.76MHz Select] TTL Logic HIGH on this pin denotes a 77.76MHz input reference clock. Tie to logic LOW if input is not 77.76MHz. RST [Reset] TTL Tie to logic LOW for normal operation; logic HIGH forces reset of internal Phase Detector & feedback dividers. FLTRP, FLTRN [Loop Filter, Pos & Neg] Analog Connect a series RC loop filter between these pins. The suggested RC values are 500 Ω and 0.1µF, as shown in the Typical Application. DISC [Disable Clock] TTL Logic HIGH on this pin disables the Retimed Reference Clock output RETRFCK); if this output is not required, it is recommended that it be disabled to reduce switching noise. A logic LOW enables the output. PIN DESCRIPTION OUTPUTS CK622P, CK622N [622 Clock Output] Differential PECL. 622.08MHz output clock from PLL B. CK155 [155 Clock Out] Single-ended PECL 155.52MHz output clock. RETRFCK [Retimed Reference Clock Out] TTL An output clock with the same frequency as the input Reference Clock (RFCK) and a 45-55% duty cycle. This output is derived by dividing the 622.08MHz output by the appropriate factor (e.g., divide by 16 for a 38.88MHz inout reference; divide by 12 for 51.84Mhz in; or divide by 8 for 77.76MHz in). POWER & GROUND VCC +5V for internal circuits. VCCO +5V for PECL outputs. GND Ground (0 volts). |
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