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SY89827LHI Datasheet(PDF) 4 Page - Micrel Semiconductor |
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SY89827LHI Datasheet(HTML) 4 Page - Micrel Semiconductor |
4 / 11 page 4 Precision Edge® SY89827L Micrel, Inc. M9999-073010 hbwhelp@micrel.com or (408) 955-1690 PIN DESCRIPTIONS Internal PinNumber PinName I/O Type P/U PinFunction 5, 6 HSTL_CLKA Input HSTL Differential clock input selected by CLK_SEL1, SEL1 and SEL2. /HSTL_CLKA Canbeleftfloatingifnotselected.Floatinginput,ifselected produces an indeterminate output. HSTL input signal requires externaltermination50Ω-to-GND. 2, 3 HSTL_CLKB Input HSTL Differential clock input selected by CLK_SEL1, SEL1 and SEL2. /HSTL_CLKB Canbeleftfloatingifnotselected.Floatinginput,ifselected produces an indeterminate output. HSTL input signal requires externaltermination50Ω-to-GND. 8,9 LVPECL_CLKA Input LVPECL 75kΩ DifferentialclockinputselectedbyCLK_SEL1,SEL1andSEL2. /LVPECL_CLKA pull-down Canbeleftfloating.Floatinginput,ifselectedproducesaLOW at output. Requires external termination. See Figure 1. 12,13 LVPECL_CLKB Input LVPECL 75kΩ DifferentialclockinputselectedbyCLK_SEL2,SEL1andSEL2. /LVPECL_CLKB pull-down Requires external termination. See Figure 1. 7 CLK_SEL1 Input LVTTL/ 11kΩ SelectsHSTL_CLKAinputwhenLOWandLVPECL_CLKA CMOS Pull-up input when HIGH. 14 CLK_SEL2 Input LVTTL/ 11kΩ SelectsHSTL_CLKBinputwhenLOWandLVPECL_CLKB CMOS Pull-up input when HIGH. 16 SEL1 Input LVTTL/ 11kΩ SelectsinputsourceCLKAwhenLOWandCLKB CMOS Pull-up when HIGH for outputs Q0 – Q9 and /Q0 – /Q9. 1 SEL2 Input LVTTL/ 11kΩ SelectsinputsourceCLKAwhenLOWandCLKB CMOS Pull-up when HIGH for outputs Q10 – Q19 and /Q10 – /Q19. 11 OE1 Input LVTTL/ 11kΩ Enableinputsynchronizedinternallytopreventglitchingofthe CMOS Pull-up Q0 – Q9 and /Q0 – /Q9 outputs. 15 OE2 Input LVTTL/ 11kΩ Enableinputsynchronizedinternallytopreventglitchingofthe CMOS Pull-up Q10 – Q19 and /Q10 – /Q19 outputs. 4 VCCI Power Core VCC connected to 3.3V supply. Bypass with 0.1µF in parallelwith0.01µFlowESRcapacitorsasclosetoVCCpinsas possible. 17, 32, 33, VCCO Power Output buffer VCC connected to 1.8V nominal supply. All VCCO 40, 41, 48, 49, 64 pins should be connected together on the PCB. Bypass with 0.1µF in parallel with 0.01µF low ESR capacitors as close to VCCO pins as possible. 10 GND Power Ground. 63, 61, 59, 57, 55 Q0 – Q9 Output HSTL Differential clock outputs from CLKA when SEL1 = LOW and 53, 51, 47, 45, 43 fromCLKBwhenSEL1=HIGH.HSTLoutputs(Qand/Q)must beterminatedwith50Ω-to-GND.Qoutputsarestaticwhen OE1=LOW.Unusedoutputpairsmaybeleftfloating. 62, 60, 58, 56, 54 /Q0 – /Q9 Output HSTL Differential clock outputs (complement) from CLKA when SEL1 = 52, 50, 46, 44, 42 LOW and from CLKB when SEL1 = HIGH. HSTL outputs (Q and /Q)mustbeterminatedwith50Ω-to-GND./Qoutputsarestatic HIGH when OE1 = LOW. Unused output pairs may be left floating. 39, 37, 35, 31, 29 Q10 – Q19 Output HSTL Differential outputs from CLKA when SEL2 = LOW and from 27, 25, 23, 21, 19 CLKB when SEL2 = HIGH. HSTL outputs (Q and /Q) must be terminatedwith50Ω-to-GND.QoutputsarestaticLOWwhen OE2=LOW.Unusedoutputpairsmaybeleftfloating. 38, 36, 34, 30, 28 /Q10 – /Q19 Output HSTL Differentialoutputs(complement)fromCLKAwhenSEL2=LOW 26, 24, 22, 20, 18 and from CLKB when SEL2 = HIGH. HSTL outputs (Q and /Q) mustbeterminatedwith50Ω-to-GND./QoutputsarestaticHIGH whenOE2=LOW.Unusedoutputpairsmaybeleftfloating. |
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