3

SY89828L

MicreL, Inc.

M9999-012208

hbwhelp@micrel.com or (408) 955-1690

PIN DESCRIPTIONS

Internal

Pin Number

Pin Name

I/O

Type

P/U

Pin Function

5, 6

LVDS_CLKA

Input

LVDS

3.5kΩ

Differential clock input selected by CLK_SEL1, SEL1 and

/LVDS_CLKA

Pull-up

SEL2. Can be left floating if not selected. Floating input, if

See Fig. 2

selected produces an indeterminate output. Has internal

100Ω termination.

2, 3

LVDS_CLKB

Input

LVDS

3.5kΩ

Differential clock input selected by CLK_SEL1, SEL1 and

/LVDS_CLKB

Pull-up

SEL2. Can be left floating if not selected. Floating input, if

See Fig. 2

selected produces an indeterminate output. Has internal

100Ω termination.

8, 9

LVPECL_CLKA

Input

LVPECL

75kΩ

Differential clock input selected by CLK_SEL1, SEL1

/LVPECL_CLKA

pull-down

and SEL2. Can be left floating. Floating input, if selected

See Fig. 1

produces a LOW at output. Requires external termination.

12, 13

LVPECL_CLKB

Input

LVPECL

75kΩ

Differential clock input selected by CLK_SEL2, SEL1

/LVPECL_CLKB

pull-down

and SEL2. Requires external termination.

See Fig. 1

7

CLK_SEL1

Input

LVTTL/

11kΩ

Selects LVDS_CLKA input when LOW and

CMOS

Pull-up

LVPECL_CLKA input when HIGH.

14

CLK_SEL2

Input

LVTTL/

11kΩ

Selects LVDS_CLKB input when LOW and

CMOS

Pull-up

LVPECL_CLKB input when HIGH.

16

SEL1

Input

LVTTL/

11kΩ

Selects input source CLKA when LOW and CLKB

CMOS

Pull-up

when HIGH for outputs Q0 – Q9 and /Q0 – /Q9.

1

SEL2

Input

LVTTL/

11kΩ

Selects input source CLKA when LOW and CLKB

CMOS

Pull-up

when HIGH for outputs Q10 – Q19 and /Q10 – /Q19.

11

OE1

Input

LVTTL/

11kΩ

Enable input synchronized internally to prevent output

CMOS

Pull-up

glitches or runt pulses.

15

OE2

Input

LVTTL/

11kΩ

Enable input synchronized internally to prevent output

CMOS

Pull-up

glitches or runt pulses.

4

VCCI

Power

Core VCC connected to 3.3V supply. Not connected to

VCCO internally. Connected to VCCO on PCB.

Bypass with 0.1µF in parallel with 0.01µF low ESR

capacitors as close to VCC pins as possible.

17, 32, 40,

VCCO

Power

Output buffer VCC connected to 3.3V suppy. Not connected

41, 49, 64

to VCCI internally. Connected to VCCI on PCB.

Bypass with 0.1µF in parallel with 0.01µF low ESR

capacitors as close to VCC pins as possible.

10

GNDI

Power

Core ground not connected to GNDO internally.

To be connected to GNDO on PCB.

33, 48

GNDO

Power

Output buffer ground not connected to GNDI internally.

To be connected to GNDI on PCB.

63, 61, 59, 57, 55

Q0 – Q9

Output

LVDS

Differential clock outputs from CLKA when SEL1 = LOW

53, 51, 47, 45, 43

and from CLKB when SEL1 = HIGH. Q outputs are static

when OE1 = LOW. Unused output pair must be terminated

with 100Ω to maintain low jitter and skew.

62, 60, 58, 56, 54

/Q0 – /Q9

Output

LVDS

Differential clock outputs (complement) from CLKA when

52, 50, 46, 44, 42

SEL1 = LOW and from CLKB when SEL1 = HIGH. /Q

outputs are static HIGH when OE1 = LOW. Unused output

pairs must be externally terminated with 100Ω to maintain

low jitter and skew.

39, 37, 35, 31, 29

Q10 – Q19

Output

LVDS

Differential outputs from CLKA when SEL2 = LOW and

27, 25, 23, 21, 19

from CLKB when SEL2 = HIGH. Q outputs are static LOW

when OE2 = LOW. Unused output pairs must be externally

terminated with 100Ω to maintain low jitter and skew.