Micrel, Inc.

SY89833AL

March 2009

3

M9999-032609-A

Pin Description

Pin Number

Pin Name

Pin Function

15, 16

1, 2

3, 4

5, 6

Q0, /Q0

Q1, /Q1

Q2, /Q2

Q3, /Q3

LVDS Differential Outputs: Normally terminated with 100Ω across the pair (Q,

/Q). See “LVDS Outputs” section, Figure 2a. Unused outputs should be

terminated with a 100Ω resistor across each pair.

8

EN

This single-ended TTL/CMOS-compatible input functions as a synchronous

output enable. The synchronous enable ensures that enable/disable will only

occur when the outputs are in a logic LOW state. Note that this input is internally

connected to a 25kΩ pull-up resistor and will default to logic HIGH state

(enabled) if left open.

9, 12

/IN, IN

Differential Input: This input pair is the differential signal input to the device.

Input accepts AC- or DC-Coupled differential signals as small as 100mV. Each

pin of the pair internally terminates to a VT pin through 50Ω. Note that this input

will default to an intermediate state if left open. Please refer to the “Input

Interface Applications” section for more details.

10

VREF-AC

Coupling the input (IN, /IN). For AC-Coupled applications, connect VREF-AC to

Applications” section for more details. Maximum sink/source current is ±1.5mA.

Due to the limited drive capability, each VREF-AC pin is only intended to drive its

respective VT pin.

11

VT

Input Termination Center-Tap: Each side of the differential input pair terminates

to the VT pin. The VT pin provides a center-tap to a termination network for

maximum interface flexibility. See “Input Interface Applications” section for more

details.

13

GND

Ground. GND pin and exposed pad must be connected to the most negative

potential of the device ground.

7, 14

VCC

Positive Power Supply: Bypass with 0.1µF//0.01µF low ESR capacitors and

place as close to each VCC pin as possible.