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LT3688IFEPBF Datasheet(PDF) 9 Page - Linear Technology |
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LT3688IFEPBF Datasheet(HTML) 9 Page - Linear Technology |
9 / 28 page LT3688 9 3688f PIN FUNCTIONS (QFN/TSSOP) CPOR1, CPOR2 (Pins 23, 21/Pins 20, 18): Place a capacitor between this pin and ground to set the power-on-reset timeout period. CWDT (Pin 24/Pin 21): Place a capacitor between this pin and ground to set the fast and slow watchdog timer periods. Exposed Pad (Pin 25/Pin 25): Ground. Tie the exposed pad directly to the ground plane. The exposed pad metal of the package provides both electrical contact to ground and good thermal contact to the printed circuit board. The device must be soldered to the circuit board for proper operation. BLOCK DIAGRAM + – + BST2 SW2 DA2 RSEN2 DISABLE Q S R RT RT SLAVE OSCILLATOR MASTER OSCILLATOR INTERNAL 0.8V REF ERROR AMP SLOPE COMP SWITCH LATCH Burst Mode OPERATION DETECT ADJUSTABLE RESET PULSE GENERATOR VC CLAMP C5 CC VIN 3.4V RC VC C4 OUT2 L2 FB2 RUN/SS2 CPOR2 2.5μA 22μA 3688 BD01 RST2 BIAS OUT1 SYNC VIN VIN EN/UVLO ON OFF + – + BST1 SW1 DA1 RSEN1 Q S R SLAVE OSCILLATOR CONFIGURATION LOGIC WATCHDOG TIMER TRANSITION DETECT SLOPE COMP SWITCH LATCH Burst Mode OPERATION DETECT ADJUSTABLE RESET PULSE GENERATOR VC CLAMP OUT1 FB1 R2 R1 C2 C3 L1 RUN/SS1 CPOR1 2.5μA 2μA 22μA 22μA RST1 CWDT WDE WDI WDO CONFIG GND THREE-STATE DECODE 80mV C1 |
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