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LC72323 Datasheet(PDF) 9 Page - Sanyo Semicon Device |
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LC72323 Datasheet(HTML) 9 Page - Sanyo Semicon Device |
9 / 13 page No. 4950-9/13 LC72323 Continued from preceding page. Pin Pin No. Functions I/O I/O circuit type HCTR LCTR ADI INT EO1 EO2 SNS HOLD RES XIN XOUT TEST1 TEST2 VDD VSS 70 71 69 66 77 78 72 67 68 1 80 2 79 31, 73 76 Universal counter input The input should be capacitor coupled. The input frequency range is from 0.4 to 12 MHz. This input can be effectively used for FM IF or AM IF counting. Universal counter input The input should be capacitor coupled for input frequencies in the range 100 to 150 kHz. Capacitor coupling is not required for input frequencies from 1 to 20 Hz. This input can be effectively used for AM IF counting. This pin can also be used as a normal input port. A/D converter input A 1.28 ms period is required for a 6-bit sequential comparison conversion. The full scale input is ((63/96) · VDD) for a data value of 3FH. External interrupt request input An interrupt is generated when the INTEN flag is set (by an SS instruction) and a falling edge is input. This pin can also be used as a normal input port. Reference frequency and programmable divider phase comparison error outputs Charge pump circuits are built in. EO1 and EO2 are the same. Input pin used to determine if a power outage has occurred in BACKUP mode This pin can also be used as a normal input port. Input pin used to force the LC72323 to HOLD mode The LC72323 goes to HOLD mode when the HOLDEN flag is set (by an SS instruction) and the HOLD input goes low. A high-breakdown voltage circuit is used so that this input can be used in conjunction with the normal power switch. System reset input This signal should be held low for 75 ms after power is first applied to effect a power-up reset. The reset starts when a low level has been input for at least six reference clock cycles. Crystal oscillator connections (4.5 MHz) A feedback resistor is built in. LSI test pins. These pins must be connected to VSS. Power supply Input Input Input Output Input Input Input Input Output — — |
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