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LC72711LW Datasheet(PDF) 3 Page - Sanyo Semicon Device |
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LC72711LW Datasheet(HTML) 3 Page - Sanyo Semicon Device |
3 / 29 page No. 6167-3/29 LC72711W, 72711LW [LC72711W] Allowable Operating Ranges: Parallel Interface at Ta = –40 to +85°C, VSS = 0 V Notes: Application designs must take the RDY signal output delay into consideration if the RDY signal is used as the CPU bus wait signal. When the RDY signal is used, the “RD low-level width” and the “Corrected output RD width” values express the basic timing (excluding the wait time) settings for the CPU bus. If the RDY signal is not used, (that is, if no wait states are inserted) the value of the RD low-level width will be 250 ns (minimum). Parameter Symbol Conditions Ratings Unit min typ max Address to RD setup tSARD A0/CL, A1/CE, A2/DI, A3, RD 20 ns RD to address hold tHARD A0/CL, A1/CE, A2/DI, A3, RD, tWRDL→250 ns –20 ns RD low-level width tWRDL1 RD 250 ns RD low-level width (when RDY is used) tWRDL2 RD 100 250 ns RD cycle wait tCYRD A0/CL, A1/CE, A2/DI, A3, RD 150 ns RDY width (Register read) tWRDY RDY 60 210 ns RD data hold tRDH RD, DATn 0 ns Address to WR setup tSAWR A0/CL, A1/CE, A2/DI, A3, WR 20 ns WR to address hold tHAWR A0/CL, A1/CE, A2/DI, A3, WR 20 ns WR cycle wait tCYWR A0/CL, A1/CE, A2/DI, A3, WR 150 ns WR low-level width tWWRL WR 200 ns WR data hold tWDH WR, DATn 0 ns RDY output delay tDRDY RD, RDY 0 30 ns Corrected output RD width tWDRD1 RD (BUSWD = L 8 bits) 300 ns RD (BUSWD = H 16 bits) 540 ns Corrected output RD width tWDRD2 RD (BUSWD = L 8 bits) 100 300 ns (when RDY is used) RD (BUSWD = H 16 bits) 300 540 ns RDY width (corrected output read) tWDRDY RDY (BUSWD = L 8 bits) 60 210 ns RDY ((BUSWD = H 16 bits) 300 490 ns DACK to DREQ delay tDREQ DREQ, DACK 260 ns DMA cycle wait tCYDM RD, DREQ 420 ns RD low-level width (DMA) tWRDM RD 300 ns |
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