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TMS320DM8168 Datasheet(PDF) 10 Page - Texas Instruments |
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TMS320DM8168 Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 312 page  TMS320DM8168, TMS320DM8167 TMS320DM8166, TMS320DM8165 SPRS614 – MARCH 2011 www.ti.com 2.3.3 ARM Cortex-A8 Interrupt Controller (AINTC) The ARM Cortex-A8 subsystem contains an interrupt controller (AINTC) that prioritizes all service requests from the system peripherals and generates either IRQ or FIQ to the ARM Cortex-A8 processor. For more details on the AINTC, see Section 7.4. 2.3.4 System Interconnect The ARM Cortex-A8 processor in connected through the arbiter to both an L3 interconnect port and a DMM port. The DMM port is 128-bits wide and provides the ARM Cortex-A8 direct access to the DDR memories, while the L3 interconnect port is 64-bits wide and provides access to the remaining device modules. 10 Device Overview Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 |
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