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CY2DL1504ZXIT Datasheet(PDF) 5 Page - Cypress Semiconductor

Part # CY2DL1504ZXIT
Description  1:4 Differential LVDS Fanout Buffer with Selectable Clock Input
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY2DL1504ZXIT Datasheet(HTML) 5 Page - Cypress Semiconductor

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CY2DL1504
Document Number: 001-56312 Rev. *E
Page 5 of 15
DC Electrical Specifications
(VDD = 3.3 V ± 5% or 2.5 V ± 5%; TA = 0 °C to 70 °C (Commercial) or –40 °C to 85 °C (Industrial))
Parameter
Description
Condition
Min
Max
Unit
IDD
Operating supply current
All LVDS outputs terminated with a load of
100
Ω[3, 4]
–61
mA
VIH1
Input high voltage,
LVDS and LVPECL input clocks,
IN0, IN0#, IN1, and IN1#
–VDD + 0.3
V
VIL1
Input low voltage,
LVDS and LVPECL input clocks,
IN0, IN0#, IN1, and IN1#
–0.3
V
VIH2
Input high voltage,
CLK_EN, IN_SEL, and OE
VDD = 3.3 V
2.0
VDD + 0.3
V
VIL2
Input low voltage,
CLK_EN, IN_SEL, and OE
VDD = 3.3 V
–0.3
0.8
V
VIH3
Input high voltage,
CLK_EN, IN_SEL, and OE
VDD = 2.5 V
1.7
VDD + 0.3
V
VIL3
Input low voltage,
CLK_EN, IN_SEL, and OE
VDD = 2.5 V
–0.3
0.7
V
VID_LVDS
[5]
LVDS input differential amplitude
See Figure 3 on page 7
0.4
0.8
V
VID_LVPECL
[5]
LVPECL input differential amplitude
See Figure 3 on page 7
0.4
1.0
V
VICM
Input common mode voltage
See Figure 3 on page 7
0.5
VDD – 0.2
V
IIH
Input high current, All inputs
Input = VDD
[6]
–150
μA
IIL
Input low current, All inputs
Input = VSS
[6]
–150
μA
VPP
LVDS differential output voltage peak
to Peak, Single-ended
VDD = 3.3 V or 2.5 V,
RTERM = 100 Ω between Q and Q# pairs
[3, 7]
250
470
mV
VOCM
LVDS differential output common
mode voltage
VDD = 3.3 V or 2.5 V,
RTERM = 100 Ω between Q and Q# pairs
[3, 7]
1.125
1.375
V
ΔV
OCM
Change in VOCM between
complementary output states
VDD = 3.3 V or 2.5 V,
RTERM = 100 Ω between Q and Q# pairs
[3, 7]
–50
mV
IOZ
Output leakage current
OE = VSS, VOUT = 0.75V – 1.75V
–15
15
μA
RP
Internal pull-up/pull-down resistance,
LVCMOS logic inputs
CLK_EN has pull-up only
IN_SEL has pull-down only
OE has pull-up only
60
140
k
Ω
CIN
Input capacitance
Measured at 10 MHz; per pin
3
pF
Notes
3. Refer to Figure 2 on page 7.
4. IDD includes current that is dissipated externally in the output termination resistors.
5. VID minimum of 400 mV is required to meet all output AC Electrical Specifications. The device is functional with VID minimum of greater than 200 mV.
6. Positive current flows into the input pin, negative current flows out of the input pin.
7. Refer to Figure 4 on page 7.
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