CY2DM1502

1:2 CML / LVPECL Input to CML Output

Fanout Buffer

Cypress Semiconductor Corporation

•

198 Champion Court

•

San Jose

•

408-943-2600

Document Number: 001-56315 Rev. *F

Revised February 25, 2011

Features

emitter-coupled logic (LVPECL) input pair distributed to two

CML output pairs

(12-kHz to 20-MHz offset)

[1]

Functional Description

The

CY2DM1502

is

an

ultra-low

noise,

low-skew,

low-propagation delay 1:2 CML or LVPECL to CML fanout buffer

targeted to meet the requirements of high-speed clock

distribution applications. The device has a fully differential

internal architecture that is optimized to achieve low additive jitter

and low skew at operating frequencies of up to 1.5 GHz.

Note

1. Input AC-coupling capacitors are required for voltage-translation applications.

Logic Block Diagram

Q0

Q0#

Q1

Q1#

IN

IN#

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