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SPC5633MF0MLQA6 Datasheet(PDF) 5 Page - Freescale Semiconductor, Inc |
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SPC5633MF0MLQA6 Datasheet(HTML) 5 Page - Freescale Semiconductor, Inc |
5 / 132 page MPC5634M Microcontroller Data Sheet, Rev. 8 Freescale Semiconductor 5 — Fetch Accelerator – Provide single cycle flash access at 80 MHz – Quadruple 128-bit wide prefetch/burst buffers – Prefetch buffers can be configured to prefetch code or data or both — Censorship protection scheme to prevent flash content visibility — Flash divided into two independent arrays, allowing reading from one array while erasing/programming the other array (used for EEPROM emulation) — Memory block: – For MPC5634M: 18 blocks (4 16 KB, 2 32 KB, 2 64 KB, 10 128 KB) – For MPC5633M: 14 blocks (4 16 KB, 2 32 KB, 2 64 KB, 6 128 KB) – For MPC5632M: 12 blocks (4 16 KB, 2 32 KB, 2 64 KB, 4 128 KB) — Hardware programming state machine • On-chip static RAM — For MPC5634M: 94 KB general purpose RAM of which 32 KB are on standby power supply — For MPC5633M: 64 KB general purpose RAM of which 24 KB are on standby power supply — For MPC5632M: 48 KB general purpose RAM of which 24 KB are on standby power supply • Boot assist module (BAM) — Enables and manages the transition of MCU from reset to user code execution in the following configurations: – Execution from internal flash memory – Execution from external memory on the calibration bus – Download and execution of code via FlexCAN or eSCI • Periodic interrupt timer (PIT) — 32-bit wide down counter with automatic reload — Four channels clocked by system clock — One channel clocked by crystal clock — Each channel can produce periodic software interrupt — Each channel can produce periodic triggers for eQADC queue triggering — One channel out of the five can be used as wake-up timer to wake device from low power stop mode • System timer module (STM) — 32-bit up counter with 8-bit prescaler — Clocked from system clock — Four-channel timer compare hardware — Each channel can generate a unique interrupt request — Designed to address AutoSAR task monitor function • Software watchdog timer (SWT) — 32-bit timer — Clock by system clock or crystal clock — Can generate either system reset or non-maskable interrupt followed by system reset — Enabled out of reset • Enhanced modular I/O system (eMIOS) — 16 timer channels (up to 14 channels in 144 LQFP) — 24-bit timer resolution — Supports a subset of the timer modes found in eMIOS on MPC5554 — 3 selectable time bases plus shared time or angle counter bus from eTPU2 — DMA and interrupt request support |
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