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CY7C1312BV18 Datasheet(PDF) 1 Page - Cypress Semiconductor |
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CY7C1312BV18 Datasheet(HTML) 1 Page - Cypress Semiconductor |
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1 / 29 page  CY7C1312BV18 CY7C1314BV18 18-Mbit QDR® II SRAM Two-Word Burst Architecture Cypress Semiconductor Corporation • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document #: 38-05619 Rev. *J Revised February 2, 2011 18-Mbit QDR® II SRAM Two-Word Burst Architecture Features ■ Separate independent read and write data ports ❐ Supports concurrent transactions ■ 250 MHz clock for high bandwidth ■ Two-word burst on all accesses ■ Double data rate (DDR) interfaces on both read and write ports (data transferred at 500 MHz) at 250 MHz ■ Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only ■ Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches ■ Echo clocks (CQ and CQ) simplify data capture in high-speed systems ■ Single multiplexed address input bus latches address inputs for both read and write ports ■ Separate port selects for depth expansion ■ Synchronous internally self timed writes ■ Available in x18, and x36 configurations ■ Full data coherency, providing most current data ■ Core VDD = 1.8 V (±0.1 V); I/O VDDQ = 1.4 V to VDD ■ Available in 165-ball FBGA package (13 × 15 × 1.4 mm) ■ Offered in both Pb-free and non Pb-free packages ■ Variable drive HSTL output buffers ■ JTAG 1149.1 compatible test access port ■ Delay lock loop (DLL) for accurate data placement Configurations CY7C1312BV18 – 1 M × 18 CY7C1314BV18 – 512 K × 36 Functional Description The CY7C1312BV18, and CY7C1314BV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR® II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has data outputs to support read operations and the write port has data inputs to support write operations. QDR II architecture has separate data inputs and data outputs to completely eliminate the need to “turn around” the data bus required with common I/O devices. Access to each port is accomplished through a common address bus. The read address is latched on the rising edge of the K clock and the write address is latched on the rising edge of the K clock. Accesses to the QDR II read and write ports are completely independent of one another. To maximize data throughput, both read and write ports are provided with DDR interfaces. Each address location is associated with two 18-bit words (CY7C1312BV18), or 36-bit words (CY7C1314BV18) that burst sequentially into or out of the device. Because data can be transferred into and out of the device on every rising edge of both input clocks (K and K and C and C), memory bandwidth is maximized while simplifying system design by eliminating bus “turn arounds”. Depth expansion is accomplished with port selects, which enables each port to operate independently. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C (or K or K in a single clock domain) input clocks. Writes are conducted with on-chip synchronous self timed write circuitry. Selection Guide Description 250 MHz 200 MHz 167 MHz Unit Maximum operating frequency 250 200 167 MHz Maximum operating current x18 800 675 600 mA x36 900 750 650 [+] Feedback |
Similar Part No. - CY7C1312BV18_11 |
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Similar Description - CY7C1312BV18_11 |
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