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CY7C1318CV18 Datasheet(PDF) 7 Page - Cypress Semiconductor

Part # CY7C1318CV18
Description  18-Mbit DDR II SRAM 2-Word Burst Architecture
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1318CV18 Datasheet(HTML) 7 Page - Cypress Semiconductor

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CY7C1318CV18, CY7C1320CV18
Document Number: 001-07160 Rev. *J
Page 7 of 29
DOFF
Input
DLL Turn Off
Active LOW. Connecting this pin to ground turns off the DLL inside the device. The timing
in the DLL turned off operation is different from that listed in this data sheet. For normal operation, this
pin can be connected to a pull up through a 10 K
 or less pull up resistor. The device behaves in DDR I
mode when the DLL is turned off. In this mode, the device can be operated at a frequency of up to 167 MHz
with DDR I timing.
TDO
Output
Test Data Out (TDO) for JTAG.
TCK
Input
Test Clock (TCK) Pin for JTAG.
TDI
Input
Test Data In (TDI) Pin for JTAG.
TMS
Input
Test Mode Select (TMS) Pin for JTAG.
NC
N/A
Not Connected to the Die. Can be tied to any voltage level.
NC/36M
N/A
Not Connected to the Die. Can be tied to any voltage level.
NC/72M
N/A
Not Connected to the Die. Can be tied to any voltage level.
NC/144M
N/A
Not Connected to the Die. Can be tied to any voltage level.
NC/288M
N/A
Not Connected to the Die. Can be tied to any voltage level.
VREF
Input-
Reference
Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs, and AC
measurement points.
VDD
Power Supply Power Supply Inputs to the Core of the Device.
VSS
Ground
Ground for the Device.
VDDQ
Power Supply Power Supply Inputs for the Outputs of the Device.
Pin Definitions (continued)
Pin Name
I/O
Pin Description
[+] Feedback


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