CY7C1380D, CY7C1382D

CY7C1380F, CY7C1382F

Document Number: 38-05543 Rev. *I

Page 7 of 33

Table 1. Pin Definitions

Name

I/O

Description

Input-

Synchronous

Address inputs used to select one of the address locations. Sampled at the rising edge of

are fed to the two-bit counter..

Input-

Synchronous

Byte write select inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM.

Sampled on the rising edge of CLK.

GW

Input-

Synchronous

Global write enable input, active LOW. When asserted LOW on the rising edge of CLK, a

BWE

Input-

Synchronous

Byte write enable input, active LOW. Sampled on the rising edge of CLK. This signal must be

asserted LOW to conduct a byte write.

CLK

Input-

Clock

Clock input. Used to capture all synchronous inputs to the device. Also used to increment the

burst counter when ADV is asserted LOW, during a burst operation.

Input-

Synchronous

Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with

only when a new external address is loaded.

Input-

Synchronous

Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction

address is loaded.

Input-

Synchronous

Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with

is loaded.

OE

Input-

Asynchronous

Output enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When

LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act

as input data pins. OE is masked during the first clock of a read cycle when emerging from a

deselected state.

ADV

Input-

Synchronous

Advance input signal, sampled on the rising edge of CLK, active LOW. When asserted, it

automatically increments the address in a burst cycle.

ADSP

Input-

Synchronous

Address strobe from processor, sampled on the rising edge of CLK, active LOW. When

asserted LOW, addresses presented to the device are captured in the address registers. A1: A0

are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is

ADSC

Input-

Synchronous

Address strobe from controller, sampled on the rising edge of CLK, active LOW. When

asserted LOW, addresses presented to the device are captured in the address registers. A1: A0

are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is

recognized.

ZZ

Input-

Asynchronous

ZZ sleep input. This active HIGH input places the device in a non-time critical sleep condition

with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin

has an internal pull down.

I/O-

Synchronous

Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered

by the rising edge of CLK. As outputs, they deliver the data contained in the memory location

specified by the addresses presented during the previous clock rise of the read cycle. The

direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs.

Power Supply Power supply inputs to the core of the device.

Ground

Ground for the core of the device.

I/O Ground

Ground for the I/O circuitry.

Note

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