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CY7C1381D Datasheet(PDF) 8 Page - Cypress Semiconductor |
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CY7C1381D Datasheet(HTML) 8 Page - Cypress Semiconductor |
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8 / 34 page  CY7C1381D/CY7C1381F CY7C1383D/CY7C1383F Document Number: 38-05544 Rev. *I Page 8 of 34 Pin Definitions Name I/O Description A0, A1, A Input Synchronous Address inputs used to select one of the address locations. Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 [4] are sampled active. A[1:0] feed the 2-bit counter. BWA, BWB BWC, BWD Input Synchronous Byte write select inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled on the rising edge of CLK. GW Input Synchronous Global write enable input, active LOW. When asserted LOW on the rising edge of CLK, a global write is conducted (all bytes are written, regardless of the values on BW[A:D] and BWE). CLK Input Clock Clock input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW, during a burst operation. CE1 Input Synchronous Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3 [4] to select or deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a new external address is loaded. CE2 Input Synchronous Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 [4] to select or deselect the device. CE2 is sampled only when a new external address is loaded. CE3 [4] Input Synchronous Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select or deselect the device. CE3 is sampled only when a new external address is loaded. OE Input Asynchronous Output enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tristated, and act as input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state. ADV Input Synchronous Advance input signal. Sampled on the rising edge of CLK. When asserted, it automatically increments the address in a burst cycle. ADSP Input Synchronous Address strobe from processor, sampled on the rising edge of CLK, active LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH. ADSC Input Synchronous Address strobe from controller, sampled on the rising edge of CLK, active LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. BWE Input Synchronous Byte write enable input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted LOW to conduct a byte write. ZZ Input Asynchronous ZZ sleep input. This active HIGH input places the device in a non time critical sleep condition with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an internal pull down. Note 4. CE3, CE2 are for TQFP and 165 FBGA packages only. 119 BGA is offered only in 1 chip enable. [+] Feedback |
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