CY7C12631KV18 datasheet(4/30 Pages) CYPRESS

Part #	CY7C12631KV18

Description	36-Mbit QDR짰 II SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)

Download	30 Pages

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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4 / 30 page

CY7C12611KV18, CY7C12761KV18

CY7C12631KV18, CY7C12651KV18

Document Number: 001-53193 Rev. *D

Page 4 of 30

Contents

Pin Configurations ........................................................... 5

165-Ball FBGA (13 x 15 x 1.4 mm) Pinout .................. 5

Functional Overview ........................................................ 9

Read Operations ......................................................... 9

Write Operations ......................................................... 9

Byte Write Operations ................................................. 9

Concurrent Transactions ............................................. 9

Depth Expansion ....................................................... 10

Programmable Impedance ........................................ 10

Echo Clocks .............................................................. 10

Valid Data Indicator (QVLD) ...................................... 10

PLL ............................................................................ 10

Application Example ...................................................... 10

IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 13

Disabling the JTAG Feature ...................................... 13

Test Access Port—Test Clock ................................... 13

Test Mode Select (TMS) ........................................... 13

Test Data-In (TDI) ..................................................... 13

Test Data-Out (TDO) ................................................. 13

Performing a TAP Reset ........................................... 13

TAP Registers ........................................................... 13

TAP Instruction Set ................................................... 13

TAP Electrical Characteristics ...................................... 16

TAP AC Switching Characteristics ............................... 17

TAP Timing and Test Conditions .................................. 17

Boundary Scan Order .................................................... 19

Power-Up Sequence in QDR II+ SRAM ......................... 20

Power-Up Sequence ................................................. 20

PLL Constraints ......................................................... 20

Maximum Ratings ........................................................... 21

Operating Range ............................................................ 21

Neutron Soft Error Immunity ......................................... 21

Electrical Characteristics .............................................. 21

DC Electrical Characteristics ..................................... 21

AC Electrical Characteristics ..................................... 22

Capacitance .................................................................... 23

Thermal Resistance ....................................................... 23

Switching Characteristics ............................................. 24

Switching Waveforms .................................................... 25

Read/Write/Deselect Sequence ................................ 25

Ordering Information ..................................................... 26

Ordering Code Definitions ......................................... 26

Package Information ...................................................... 27

Document Conventions ................................................. 28

Acronyms Used ......................................................... 28

Units of Measure ....................................................... 28

Document History Page ................................................. 29

Sales, Solutions, and Legal Information ...................... 30

Worldwide Sales and Design Support ....................... 30

Products .................................................................... 30

PSoC Solutions ......................................................... 30

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