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CY8C20434-12LQXI Datasheet(PDF) 1 Page - Cypress Semiconductor |
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CY8C20434-12LQXI Datasheet(HTML) 1 Page - Cypress Semiconductor |
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1 / 47 page  CY8C20134, CY8C20234, CY8C20334 CY8C20434, CY8C20534, CY8C20634 PSoC® Programmable System-on-Chip™ Cypress Semiconductor Corporation • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document Number: 001-05356 Rev. *N Revised February 16, 2011 PSoC® Programmable System-on-Chip™ Features ■ Low power CapSense® block ❐ Configurable capacitive sensing elements ❐ Supports combination of CapSense buttons, sliders, touchpads, and proximity sensors ■ Powerful Harvard-architecture processor ❐ M8C processor speeds running up to 12 MHz ❐ Low power at high speed ❐ Operating voltage: 2.4 V to 5.25 V ❐ Industrial temperature range: –40 °C to +85 °C ■ Flexible on-chip memory ❐ 8 KB flash program storage 50,000 erase/write cycles ❐ 512-Bytes SRAM data storage ❐ Partial flash updates ❐ Flexible protection modes ❐ Interrupt controller ❐ In-system serial programming (ISSP) ■ Complete development tools ❐ Free development tool (PSoC Designer™) ❐ Full-featured, in-circuit emulator, and programmer ❐ Full-speed emulation ❐ Complex breakpoint structure ❐ 128 KB trace memory ■ Precision, programmable clocking ❐ Internal ±5.0% 6- / 12-MHz main oscillator ❐ Internal low speed oscillator at 32 kHz for watchdog and sleep ■ Programmable pin configurations ❐ Pull-up, high Z, open-drain, and CMOS drive modes on all GPIOs ❐ Up to 28 analog inputs on all GPIOs ❐ Configurable inputs on all GPIOs ❐ 20-mA sink current on all GPIOs ❐ Selectable, regulated digital I/O on port 1 • 3.0 V, 20 mA total port 1 source current • 5 mA strong drive mode on port 1 versatile analog mux ❐ Common internal analog bus ❐ Simultaneous connection of I/O combinations ❐ Comparator noise immunity ❐ Low-dropout voltage regulator for the analog array ■ Additional system resources ❐ Configurable communication speeds •I2C: selectable to 50 kHz, 100 kHz, or 400 kHz • SPI: configurable between 46.9 kHz and 3 MHz ❐ I2C slave ❐ SPI master and SPI slave ❐ Watchdog and sleep timers ❐ Internal voltage reference ❐ Integrated supervisory circuit SRAM 512 Bytes System Bus Interrupt Controller 6/12 MHz Internal Main Oscillator Global Analog Interconnect PSoC CORE CPU Core (M8C) SROM Flash 8K SYSTEM RESOURCES ANALOG SYSTEM Analog Ref. I2C Slave/SPI Master-Slave POR and LVD System Resets Port 1 Port 0 Sleep and Watchdog Analog Mux Port 3 Port 2 CapSense Block Config LDO Logic Block Diagram [+] Feedback |
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