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CY8C21534-24PVXA Datasheet(PDF) 3 Page - Cypress Semiconductor |
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CY8C21534-24PVXA Datasheet(HTML) 3 Page - Cypress Semiconductor |
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3 / 37 page  CY8C21334, CY8C21534 Document Number: 001-12550 Rev. *H Page 3 of 37 PSoC Functional Overview The PSoC family consists of many devices with on-chip controllers. These devices are designed to replace multiple traditional microcontroller unit (MCU)-based system components with one, low-cost single-chip programmable component. A PSoC device includes configurable blocks of analog and digital logic, and programmable interconnect. This architecture makes it possible for you to create customized peripheral configurations, to match the requirements of each individual application. Additionally, a fast CPU, flash program memory, SRAM data memory, and configurable I/O are included in a range of convenient pinouts. The PSoC architecture, as illustrated in the “Logic Block Diagram” on page 1, comprises of four main areas: the core, the system resources, the digital system, and the analog system. Configurable global bus resources allow all the device resources to be combined into a complete custom system. Each CY8C21x34 PSoC device includes four digital blocks and four analog blocks. Depending on the PSoC package, up to 24 GPIOs are also included. The GPIOs provide access to the global digital and analog interconnects. The PSoC Core The PSoC core is a powerful engine that supports a rich instruction set. It encompasses SRAM for data storage, an interrupt controller, sleep, and watchdog timers, and an internal main oscillator (IMO) and internal low-speed oscillator (ILO). The CPU core, called the M8C, is a powerful processor with speeds up to 24 MHz. The M8C is a four-million instructions per second (MIPS) 8-bit Harvard-architecture microprocessor. System Resources provide additional capability, such as digital clocks for increased flexibility, I2C functionality for implementing an I2C master, slave, or multi-master, an internal voltage reference that provides an absolute value of 1.3 V to a number of PSoC subsystems, and various system resets supported by the M8C. The Digital System is composed of an array of digital PSoC blocks, which can be configured into any number of digital peripherals. The digital blocks can be connected to the GPIO through a series of global buses that can route any signal to any pin. This frees designs from the constraints of a fixed peripheral controller. The Analog System is composed of four analog PSoC blocks, supporting comparators and analog-to-digital conversion with up to 10 bits of precision. The Digital System The digital system is composed of four digital PSoC blocks. Each block is an 8-bit resource that can be used alone or combined with other blocks to form 8-, 16-, 24-, and 32-bit peripherals, which are called user modules. Digital peripheral configurations include those listed. ■ PWMs (8- to 32-bit) ■ PWMs with dead band (8- to 24-bit) ■ Counters (8- to 32-bit) ■ Timers (8- to 32-bit) ■ Full or half-duplex 8-bit UART with selectable parity ■ SPI master and slave ■ I 2C master, slave, or multi-master (implemented in a dedicated I2C block) ■ Cyclical redundancy checker/generator (16-bit) ■ Infrared Data Association (IrDA) ■ PRS generators (8- to 32-bit) The digital blocks can be connected to any GPIO through a series of global buses that can route any signal to any pin. The buses also allow for signal multiplexing and for performing logic operations. This configurability frees your designs from the constraints of a fixed peripheral controller. Figure 1. Digital System Block Diagram Digital blocks are provided in rows of four, where the number of blocks varies by PSoC device family. This allows you the optimum choice of system resources for your application. Family resources are shown in Table 1 on page 5. DIGITAL SYSTEM To System Bus Digital Clocks From Core Digital PSoC Block Array To Analog System 8 8 8 8 Row 0 DBB00 DBB01 DCB02 DCB03 4 4 GIE[7:0] GIO[7:0] GOE[7:0] GOO[7:0] Global Digital Interconnect Port 3 Port 2 Port 1 Port 0 [+] Feedback |
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