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CY14B512Q1 Datasheet(PDF) 10 Page - Cypress Semiconductor

Part # CY14B512Q1
Description  512-Kbit (64 K 횞 8) Serial (SPI) nvSRAM
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY14B512Q1 Datasheet(HTML) 10 Page - Cypress Semiconductor

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CY14B512Q1
CY14B512Q2
CY14B512Q3
Document #: 001-53873 Rev. *E
Page 10 of 27
Status Register
The Status Register bits are listed in Table 3. The Status Register consists of a Ready bit (RDY) and data protection bits BP1, BP0,
WEN, and WPEN. The RDY bit can be polled to check the Ready or Busy status while a nvSRAM STORE or Software RECALL cycle
is in progress. The Status Register can be modified by WRSR instruction and read by RDSR instruction. However, only the WPEN,
BP1, and BP0 bits of the Status Register can be modified by using the WRSR instruction. The WRSR instruction has no effect on
WEN and RDY bits. The default value shipped from the factory for WEN, BP0, BP1, bits 4-6 and WPEN bits is ‘0’.
Read Status Register (RDSR) Instruction
The RDSR instruction provides access to the Status Register.
This instruction is used to probe the Write Enable status of the
device or the Ready status of the device. RDY bit is set by the
device to ‘1’ whenever a STORE or Software RECALL cycle is
in progress. The block protection and WPEN bits indicate the
extent of protection employed.
This instruction is issued after the falling edge of CS using the
opcode for RDSR.
Write Status Register (WRSR) Instruction
The WRSR instruction enables the user to write to the Status
Register. However, this instruction cannot be used to modify bit
0 and bit 1 (RDY and WEN). The BP0 and BP1 bits can be used
to select one of four levels of block protection. Further, WPEN bit
must be set to ‘1’ to enable the use of write protect (WP) pin.
WRSR instruction is a write instruction and needs writes to be
enabled (WEN bit set to ‘1’) using the WREN instruction before
it is issued. The instruction is issued after the falling edge of CS
using the opcode for WRSR followed by 8 bits of data to be
stored in the Status Register. Since only bits 2, 3, and 7 can be
modified by WRSR instruction; therefore, it is recommended to
leave the bits 4-6 as ‘0’ while writing to the Status Register.
Note In CY14B512Q1/CY14B512Q2/CY14B512Q3, the values
written to Status Register are saved to nonvolatile memory only
after a STORE operation. If AutoStore is disabled (or while using
CY14B512Q1), any modifications to the Status Register must be
secured by performing a Software STORE operation.
Note CY14B512Q2 does not have WP pin. Any modification to
bit 7 of the Status Register has no effect on the functionality of
CY14B512Q2.
Table 4. Status Register Format
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WPEN (0)
X(0)
X(0)
X(0)
BP1 (0)
BP0 (0)
WEN(0)
RDY
Table 5. Status Register Bit Definition
Bit
Definition
Description
Bit 0 (RDY)
Ready
Read only bit indicates the ready status of device to perform a memory access. This bit is
set to ‘1’ by the device while a STORE or Software RECALL cycle is in progress.
Bit 1 (WEN)
Write Enable
WEN indicates if the device is Write Enabled. This bit defaults to ‘0’ (disabled) on power-up.
WEN = '1' --> Write Enabled
WEN = '0' --> Write Disabled
Bit 2 (BP0)
Block protect bit ‘0’
Used for block protection. For details see Table 6 on page 11.
Bit 3 (BP1)
Block protect bit ‘1’
Used for block protection. For details see Table 6 on page 11.
Bit 4-6
Don’t care
Bits are writable and volatile. On power-up, bits are written with ‘0’.
Bit 7 (WPEN) Write protect enable bit Used for enabling the function of Write Protect Pin (WP). For details see Table 7 on page 12.
Figure 7. Read Status Register (RDSR) Instruction Timing
CS
SCK
SO
0123456
7
SI
0000
0
1
0
0
1
MSB
LSB
HI-Z
0
12345
6
7
Data
LSB
D0
D1
D2
D3
D4
D5
D6
MSB
D7
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