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CY14C101I Datasheet(PDF) 5 Page - Cypress Semiconductor |
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CY14C101I Datasheet(HTML) 5 Page - Cypress Semiconductor |
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5 / 42 page  PRELIMINARY CY14C101I CY14B101I, CY14E101I Document #: 001-54391 Rev. *C Page 5 of 42 Data Validity The data on the SDA line must be stable during the HIGH period of the clock. The state of the data line can only change when the clock on the SCL line is LOW for the data to be valid. There are only two conditions under which the SDA line may change state with SCL line held HIGH: START and STOP condition. The START and STOP conditions are generated by the master to signal the beginning and end of a communication sequence on the I2C bus. START Condition (S) A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition. Every transaction in I2C begins with the master generating a START condition. STOP Condition (P) A LOW to HIGH transition on the SDA line while SCL is HIGH indicates a STOP condition. This condition indicates the end of the ongoing transaction. START and STOP conditions are always generated by the master. The bus is considered to be busy after the START condition. The bus is considered to be free again after the STOP condition. Repeated START (Sr) If a Repeated START condition is generated instead of a STOP condition, the bus continues to be busy. The ongoing transaction on the I2C lines is stopped and the bus waits for the master to send a slave ID for communication to restart. Figure 2. System Configuration using Serial (I2C) nvSRAM Vcc SDA SCL Vcc Vcc 1 A 1 A 1 A A2 A2 A2 L C S L C S L C S SDA A D S A D S P W P W P W CY14X101I CY14X101I CY14X101I #0 #1 #3 Microcontroller RPmin = (VCC - VOLmax) / IOL RPmax = tr / Cb Figure 3. START and STOP Conditions full pagewidth SDA SCL P STOP Condition SDA SCL S START Condition [+] Feedback |
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