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CY14E101J Datasheet(PDF) 3 Page - Cypress Semiconductor |
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CY14E101J Datasheet(HTML) 3 Page - Cypress Semiconductor |
3 / 32 page PRELIMINARY CY14C101J CY14B101J, CY14E101J Document #: 001-54050 Rev. *D Page 3 of 32 Pinouts Figure 1. Pin Diagram – 8-Pin SOIC Figure 2. Pin Diagram – 16-Pin SOIC Table 1. Pin Definitions Pin Name I/O Type Description SCL Input Clock. Runs at speeds up to a maximum of fSCL. SDA Input/Output I/O. Input/Output of data through I2C interface. WP Input Write Protect. Protects the memory from all writes. This pin is internally pulled LOW and hence can be left open if not connected. A2-A1 Input Slave Address. Defines the slave address for I2C. This pin is internally pulled LOW and hence can be left open if not connected. HSB Input/Output Hardware STORE Busy Output: Indicates busy status of nvSRAM when LOW. After each Hardware and Software STORE operation HSB is driven HIGH for a short time (tHHHD) with standard output high current and then a weak internal pull-up resistor keeps this pin HIGH (External pull up resistor connection optional). Input: Hardware STORE implemented by pulling this pin LOW externally. VCAP Power supply AutoStore capacitor. Supplies power to the nvSRAM during power loss to STORE data from the SRAM to nonvolatile elements. If not required, AutoStore must be disabled and this pin left as no connect. It must never be connected to ground. NC No connect No connect. This pin is not connected to the die. VSS Power supply Ground. VCC Power supply Power supply. WP SCL 1 2 3 4 5 NC 8 7 6 V CC SDA A1 A2 V Top View not to scale CY14X101J1 SS WP SCL 1 2 3 4 5 8 7 6 V CC SDA A1 A2 Top View not to scale CY14X101J2 V CAP VSS [2] WP V CAP 1 2 3 4 5 6 7 8 9 10 11 12 13 NC 16 15 14 VCC A2 SDA SCL A1 HSB NC Top View not to scale VSS NC NC NC NC NC CY14X101J3 [2] Note 2. This pin is reserved for lower densities. [+] Feedback |
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