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CY14E101I-SFXI Datasheet(PDF) 6 Page - Cypress Semiconductor |
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CY14E101I-SFXI Datasheet(HTML) 6 Page - Cypress Semiconductor |
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6 / 42 page  PRELIMINARY CY14C101I CY14B101I, CY14E101I Document #: 001-54391 Rev. *C Page 6 of 42 Byte Format Each operation in I2C is done using 8-bit words. The bits are sent in MSB first format on SDA line and each byte is followed by an ACK signal by the receiver. An operation continues till a NACK is sent by the receiver or STOP or Repeated START condition is generated by the master The SDA line must remain stable when the clock (SCL) is HIGH except for a START or STOP condition. Acknowledge /No-acknowledge After transmitting one byte of data or address, the transmitter releases the SDA line. The receiver pulls the SDA line LOW to acknowledge the receipt of the byte. Every byte of data trans- ferred on the I2C bus needs a response with an ACK signal by the receiver to continue the operation. Failing to do so is considered as a NACK state. NACK is the state where receiver does not acknowledge the receipt of data and the operation is aborted. NACK can be generated by master during a READ operation in following cases: ■ The master did not receive valid data due to noise. ■ The master generates a NACK to abort the READ sequence. After a NACK is issued by the master, nvSRAM slave releases control of the SDA pin and the master is free to generate a Repeated START or STOP condition. NACK can be generated by nvSRAM slave during a WRITE operation in these cases: ■ nvSRAM did not receive valid data due to noise. ■ The master tries to access write protected locations on the nvSRAM. Master must restart the communication by generating a STOP or Repeated START condition. Figure 4. Data Transfer on the I2C Bus handbook, full pagewidth Sr or P SDA Sr P SCL STOP or Repeated START condition S or Sr START or Repeated START condition 1 2 3 - 8 9 ACK 9 ACK 78 12 MSB Acknowledgement signal from slave Byte complete, interrupt within slave Clock line held LOW while interrupts are serviced Acknowledgement signal from receiver Figure 5. Acknowledge on the I2C Bus handbook, full pagewidth S START Condition 9 8 2 1 Clock pulse for acknowledgement Not acknowledge (A) Acknowledge (A) DATA OUTPUT BY MASTER DATA OUTPUT BY SLAVE SCL FROM MASTER [+] Feedback |
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