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CY14E101PA-SF104XIT Datasheet(PDF) 5 Page - Cypress Semiconductor

Part # CY14E101PA-SF104XIT
Description  1-Mbit (128 K 횞 8) Serial (SPI) nvSRAM with Real Time Clock
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY14E101PA-SF104XIT Datasheet(HTML) 5 Page - Cypress Semiconductor

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PRELIMINARY
CY14C101PA
CY14B101PA
CY14E101PA
Document #: 001-54392 Rev. *C
Page 5 of 44
to complete the Store. This corrupts the data stored in the
nvSRAM and Status Register. To resume normal functionality,
the WRSR instruction must be issued to update the nonvolatile
bits BP0, BP1, and WPEN in the Status Register.
Figure 2 shows the proper connection of the storage capacitor
(VCAP) for AutoStore operation. Refer to DC Electrical Charac-
teristics on page 32 for the size of the VCAP.
Figure 2. AutoStore Mode
Software STORE Operation
Software STORE allows the user to trigger a STORE operation
through a special SPI instruction. STORE operation is initiated
by executing STORE instruction regardless of whether or not a
write has been performed since the last NV operation.
A STORE cycle takes tSTORE time to complete, during which all
the memory accesses to nvSRAM are inhibited. The RDY bit of
the Status Register or the HSB pin may be polled to find the
Ready/Busy status of the nvSRAM. After the tSTORE cycle time
is completed, the SRAM is activated again for read and write
operations.
Hardware STORE and HSB pin Operation
The HSB pin in CY14X101PA is used to control and
acknowledge STORE operations. If no STORE/RECALL is in
progress, this pin can be used to request a Hardware STORE
cycle. When the HSB pin is driven LOW, the CY14X101PA
conditionally initiates a STORE operation after tDELAY duration.
A STORE cycle starts only if a write to the SRAM has been
performed since the last STORE or RECALL cycle. Reads and
Writes to the memory are inhibited for tSTORE duration or as long
as HSB pin is LOW. The HSB pin also acts as an open drain
driver (internal 100 k
Ω weak pull up resistor) that is internally
driven LOW to indicate a busy condition when the STORE
(initiated by any means) is in progress.
Note After each Hardware and Software STORE operation, HSB
is driven HIGH for a short time (tHHHD) with standard output high
current and then remains HIGH by an internal 100 k
Ω pull-up
resistor.
Note For successful last data byte STORE, a hardware STORE
should be initiated at least one clock cycle after the last data bit
D0 is received.
Upon completion of the STORE operation, the nvSRAM memory
access is inhibited for tLZHSB time after HSB pin returns HIGH.
The HSB pin must be left unconnected if not used.
RECALL Operation
A RECALL operation transfers the data stored in the nonvolatile
QuantumTrap elements to the SRAM. In CY14X101PA, a
RECALL may be initiated in two ways: Hardware RECALL,
initiated on power-up and Software RECALL, initiated by a SPI
RECALL instruction.
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared. Next, the nonvolatile information is transferred into the
SRAM cells. All memory accesses are inhibited while a RECALL
cycle is in progress. The RECALL operation does not alter the
data in the nonvolatile elements.
Hardware RECALL (Power Up)
During power-up, when VCC crosses VSWITCH, an automatic
RECALL sequence is initiated, which transfers the content of
nonvolatile memory on to the SRAM.
A Power Up RECALL cycle takes tFA time to complete and the
memory access is disabled during this time. HSB pin is used to
detect the Ready status of the device.
Software RECALL
Software RECALL allows you to initiate a RECALL operation to
restore the content of nonvolatile memory on to the SRAM. In
CY14X101PA, this can be done by issuing a RECALL instruction
in SPI.
A Software RECALL takes tRECALL time to complete during
which all memory accesses to nvSRAM are inhibited. The
controller must provide sufficient delay for the RECALL operation
to complete before issuing any memory access instructions.
Disabling and Enabling AutoStore
If the application does not require the AutoStore feature, it can
be disabled in CY14X101PA by using the ASDISB instruction. If
this is done, the nvSRAM does not perform a STORE operation
at power-down.
AutoStore can be re enabled by using the ASENB instruction.
However, these operations are not nonvolatile and if you need
this setting to survive the power cycle, a STORE operation must
be performed following AutoStore Disable or Enable operation.
Note CY14X101PA comes from the factory with AutoStore
Enabled.
Note If AutoStore is disabled and VCAP is not required, then the
VCAP pin must be left open. The VCAP pin must never be
connected to ground. The Power Up RECALL operation cannot
be disabled in any case.
0.1uF
VCC
VCAP
CS
VCAP
VSS
VCC
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