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CY23FS08OXIT Datasheet(PDF) 1 Page - Cypress Semiconductor |
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CY23FS08OXIT Datasheet(HTML) 1 Page - Cypress Semiconductor |
1 / 15 page CY23FS08 Failsafe™ 2.5 V/3.3 V Zero Delay Buffer Cypress Semiconductor Corporation • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document Number: 38-07518 Rev. *F Revised January 7, 2011 Features ■ Internal DCXO for continuous glitch-free operation ■ Zero input-output propagation delay ■ 100 ps typical output cycle-to-cycle jitter ■ 110 ps typical output-output skew ■ 1 MHz to 200 MHz reference input ■ Supports industry standard input crystals ■ 200 MHz (commercial), 166 MHz (industrial) outputs ■ 5 V-tolerant inputs ■ Phase-locked loop (PLL) bypass mode ■ Dual reference inputs ■ 28-pin SSOP ■ Split 2.5 V or 3.3 V output power supplies ■ 3.3 V core power supply ■ Industrial temperature available Functional Description The CY23FS08 is a FailSafe™ Zero Delay Buffer with two reference clock inputs and eight phase-aligned outputs. The device provides an optimum solution for applications where continuous operation is required in the event of a primary clock failure. Continuous, glitch-free operation is achieved by using a DCXO, which serves as a redundant clock source in the event of a reference clock failure by maintaining the last frequency and phase information of the reference clock. The unique feature of the CY23FS08 is that the DCXO is in fact the primary clocking source, which is synchronized (phase-aligned) to the external reference clock. When this external clock is restored, the DCXO automatically resynchronizes to the external clock. The frequency of the crystal connected to the DCXO, must be chosen to be an integer factor of the frequency of the reference clock. This factor is set by four select lines: S[4:1]. see Table 2. The CY23FS08 has three split power supplies; one for core, another for Bank A outputs, and the third for Bank B outputs. Each output power supply, except VDDC can be connected to either 2.5 V or 3.3 V. VDDC is the power supply pin for internal circuits and must be connected to 3.3 V. CLKA[1:4] CLKB[1:4] DCXO Decoder 4 FailsafeTM Block PLL XIN XOUT 4 4 REF2 FBK S[4:1] FAIL# /SAFE REF1 REFSEL Logic Block Diagram [+] Feedback |
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