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CY22050 Datasheet(PDF) 5 Page - Cypress Semiconductor |
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CY22050 Datasheet(HTML) 5 Page - Cypress Semiconductor |
5 / 11 page CY22050, CY220501 Document #: 38-07006 Rev. *I Page 5 of 11 Reference Crystal Input The input crystal oscillator of the CY22050 is an important feature because of the flexibility it allows the user in selecting a crystal as a reference clock source. The oscillator inverter has programmable gain, allowing for maximum compatibility with a reference crystal, based on manufacturer, process, performance, and quality. The value of the input load capacitors is determined by eight bits in a programmable register. Total load capacitance is determined by the formula: CapLoad = (CL – CBRD – CCHIP)/0.09375 pF In CyClocksRT, enter the crystal capacitance (CL). The value of CapLoad is determined automatically and programmed into the CY22050. If you require greater control over the CapLoad value, consider using the CY22150 for serial configuration and control of the input load capacitors. For an external clock source, the default is 0. Input load capacitors are placed on the CY22050 die to reduce external component cost. These capacitors are true parallel-plate capacitors, designed to reduce the frequency shift that occurs when non-linear load capacitance is affected by load, bias, supply, and temperature changes. Crystal Drive Level and Power Crystals are specified to accept a maximum drive level. Generally, larger crystals can accept more power. The drive level specification in the table below is a general upper bound for the power driven by the oscillator circuit in the CY22050. For a given voltage swing, power dissipation in the crystal is proportional to ESR and proportional to the square of the crystal frequency. (Note that actual ESR is sometimes much less than the value specified by the crystal manufacturer.) Power is also almost proportional to the square of CL. Power can be reduced to less than the DL specification in the table below by selecting a reduced frequency crystal with low CL and low R1 (ESR). Note 3. Rated for 10 years Absolute Maximum Conditions Parameter Description Min Max Unit VDD Supply Voltage –0.5 7.0 V VDDL I/O Supply Voltage –0.5 7.0 V TS Storage Temperature[3] –65 125 °C TJ Junction Temperature 125 °C Package Power Dissipation—Commercial Temp 450 mW Package Power Dissipation—Industrial Temp 380 mW Digital Inputs AVSS – 0.3 AVDD + 0.3 V Digital Outputs referred to VDD VSS – 0.3 VDD + 0.3 V Digital Outputs referred to VDDL VSS – 0.3 VDDL +0.3 V ESD Static Discharge Voltage per MIL-STD-833, Method 3015 2000 V Recommended Operating Conditions Parameter Description Min Typ. Max Unit VDD Operating Voltage 3.135 3.3 3.465 V VDDLHI Operating Voltage 3.135 3.3 3.465 V VDDLLO Operating Voltage 2.375 2.5 2.625 V TAC Ambient Commercial Temp 0 70 °C TAI Ambient Industrial Temp –40 85 °C CLOAD Max. Load Capacitance VDD/VDDL = 3.3 V 15 pF CLOAD Max. Load Capacitance VDDL = 2.5 V 15 pF fREFD Driven REF 1 133 MHz fREFC Crystal REF 8 30 MHz tPU Power up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) 0.05 500 ms [+] Feedback |
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