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CY22050KFI Datasheet(PDF) 4 Page - Cypress Semiconductor |
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CY22050KFI Datasheet(HTML) 4 Page - Cypress Semiconductor |
4 / 11 page CY22050, CY220501 Document #: 38-07006 Rev. *I Page 4 of 11 CY22050 Frequency Calculation The CY22050 is an extremely flexible clock generator with up to six individual outputs, generated from an integrated PLL. There are four variables used to determine the final output frequency. They are: the input REF, the P and Q dividers, and the post divider. The three basic formulas for determining the final output frequency of a CY22150-based design are: ■ CLK = ((REF * P)/Q)/Post Divider ■ CLK = REF/Post Divider ■ CLK = REF The basic PLL block diagram is shown in Figure 2. Each of the six clock outputs has a total of seven output options available to it. There are six post divider options: /2 (two of these), /3, /4, /DIV1N, and DIV2N. DIV1N and DIV2N are separately calculated and can be independent of each other. The post divider options can be applied to the calculated PLL frequency or to the REF directly. In addition to the six post divider options, the seventh option bypasses the PLL and passes the REF directly to the crosspoint switch matrix. Clock Output Settings: Crosspoint Switch Matrix Each of the six clock outputs can come from any of seven unique frequency sources. The crosspoint switch matrix defines which source is attached to each individual clock output. Although it may seem that there are an unlimited number of divider options, there are several rules that must be taken into account when selecting divider options. Figure 2. Basic PLL Block Diagram Table 2. Clock Output Definition Clock Output Divider Definition and Notes None Clock output source is the reference input frequency /DIV1N Clock output uses a generated /DIV1N option from Divider Bank 1. Allowable values for DIV1N are 4 to 127. If Divider Bank 1 is not being used, set DIV1N to 8. /2 Clock output uses a fixed /2 option from Divider Bank 1. If this option is used, DIV1N must be divisible by 4. /3 Clock output uses a fixed /3 option from Divider Bank 1. If this option is used, set DIV1N to 6. /DIV2N Clock output uses a generated /DIV2N option from Divider Bank 2. Allowable values for DIV2N are 4 to 127. If Divider Bank 2 is not being used, set DIV2N to 8. /2 Clock output uses a fixed /2 option from Divider Bank 2. If this option is used, DIV2N must be divisible by 4. /4 Clock output 2 uses a fixed /4 option from Divider Bank 2. If this option is used, DIV2N must be divisible by 8. Q VCO P /2 /3 /2 LCLK1 LCLK2 LCLK3 LCLK4 CLK5 CLK6 Crosspoint Switch REF PFD Divider Bank 1 /4 Divider Bank 2 /DIV1N /DIV2N Matrix [+] Feedback |
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