7

Integrated

Circuit

Systems, Inc.

ICS9LPRS545

Datasheet

1479A—07/28/09

Electrical Characteristics - USB48MHz

PARAMETER

SYMBOL

CONDITIONS

MIN

MAX

UNITS NOTES

Long Accuracy

ppm

see Tperiod min-max values

-100

100

ppm

2,4

Clock period

48.00MHz output nominal

20.83125

20.83542

ns

2,3

Absolute min/max period

48.00MHz output nominal

20.48125

21.18542

ns

2

CLK High Time

8.216563

11.15198

V

CLK Low time

7.816563

10.95198

V

Output High Voltage

2.4

V

Output Low Voltage

0.55

V

-29

mA

-23

mA

29

mA

27

mA

Rising Edge Slew Rate

Measured from 0.8 to 2.0 V

1

2

V/ns

1

Falling Edge Slew Rate

Measured from 2.0 to 0.8 V

1

2

V/ns

1

Duty Cycle

45

55

%

2

Jitter, Cycle to cycle

350

ps

2

Output Low Current

Output High Current

Electrical Characteristics - REF-14.318MHz

PARAMETER

SYMBOL

CONDITIONS

MIN

MAX

UNITS Notes

Long Accuracy

ppm

see Tperiod min-max values

-100

100

ppm

2, 4

Clock period

Tperiod

14.318MHz output nominal

69.82033

69.86224

ns

2, 3

Absolute min/max period

Tabs

14.318MHz output nominal

69.83400

70.84800

ns

2

CLK High Time

THIGH

29.97543

38.46654

V

CLK Low time

TLOW

29.57543

38.26654

V

Output High Voltage

VOH

IOH = -1 mA

2.4

V

Output Low Voltage

VOL

IOL = 1 mA

0.4

V

Output High Current

IOH

VOH @MIN = 1.0 V,

VOH@MAX = 3.135 V

-33

-33

mA

Output Low Current

IOL

VOL @MIN = 1.95 V,

VOL @MAX = 0.4 V

30

38

mA

Rising Edge Slew Rate

tSLR

Measured from 0.8 to 2.0 V

1

4

V/ns

1

Falling Edge Slew Rate

tFLR

Measured from 2.0 to 0.8 V

1

4

V/ns

1

Duty Cycle

dt1

VT = 1.5 V

45

55

%

2

Jitter, Cycle to cycle

tjcyc-cyc

VT = 1.5 V

1000

ps

2

NOTES on SE outputs: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production).

Clock Jitter Specs - Low Power Differential Outputs

PARAMETER

SYMBOL

CONDITIONS

MIN

MAX

UNITS NOTES

CPU Jitter - Cycle to Cycle

CPUJC2C

Differential Measurement

85

ps

1

SRC Jitter - Cycle to Cycle

SRCJC2C

Differential Measurement

125

ps

1,2

DOT Jitter - Cycle to Cycle

DOTJC2C

Differential Measurement

250

ps

1

performance will be somewhat degraded. The receiver EMTS (chispet or CPU) will have the rece

componnet test board under quiet condittions with all outputs on. Jitter analysis is performed using a standardized tool provided by the PCI SIG or equivalent. Measurement

methodology is as defined by the PCI SIG.

NOTES on DIF Output Jitter: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production).