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Of primary concern to the designer is selecting a loop filter that insures lock-in, stability and provides adequate filtering of the

input signal. For low input frequencies, a good starting point for the loop filter bandwidth is 10 Hz (typical). An example would

be translating an 8 kHz signal to 44.736 MHz. Figures 8 and 9 show 8kHz to 44.736 MHz and 8kHz to 19.440 MHz frequency

translation designs. For high input frequencies, a good starting point for the loop filter bandwidth is 100 ppm times the input

frequency.

It’s fairly easy to set a low loop bandwidth for large frequency translations such as 8kHz to 44.736MHz, but becomes more difficult

for clock smoothing applications such as 19.440 MHz input and 19.440MHz output. In this example, 100ppm * 19.440MHz is

approximately 2kHz and this loop filter bandwidth may be too high to adequately reject jitter. A good way to resolve this is to

lower the DATAIN frequency such as dividing the input frequency down. The loop filter bandwidth becomes lower since 100ppm *

DATAIN is lowered. Figure 11 shows an example for clock smoothing on a relatively high input frequency signal and maintaining a

wide lock range.

There is no known accurate formula for calculating acquisition time and so the best way to provide realisitc figures is to measure

the lock time for a CD-700. By measuring the control voltage settling time, acquisiton time was measured in the range of 3-5

seconds for applications such as 8kHz to 34.368 MHz frequency translation which is similar to the application in Figures 8 and 9,

to sub 10 milliseconds for NRZ data patterns such as Figure 10. It may be tempting to reduce the damping factor to 0.7 or 1.0 in

order to improve acquisition time; but, it degrades stability and will not signifigantly improve acquisition time. A damping factor

of 4 is fairly conservative and allows for excellent stability.

Some general quidelines for selecting the loop filter elements include: Values should be less than 1Megohm and at least 10kohm

between the PHO and OPN, the capacitor should be low leakage and a polarized capacitor is acceptable, the R/C’s should be

located physically close to the CD-700 .The loop filter software available on the web site was written for 5 volt operation. A simple

way to calculate values for 3.3 volt operation is to multiply the data density by 0.66 (3.3V / 5V).

SPICE models are another design aid. In most cases a new PLL CD-700 design is calculated by using the software and verified with

SPICE models. The simple active SPICE model is shown in Figure 7.

Loop filter values can be modified to suit the system requirements and application. There are many excellent references on

designing PLL’s, such as “Phase-Locked Loops, Theory, Design and Applications”, by Roland E Best (McGraw-Hill).

Figure 7. SPICE Model

*****CD-700 ac Loop model

vi 1 0 ac 1

ri 1 0 1k

*****Phase Detector

e1 2 0 1 0 1

(for closed loop response use: e1 2 0 1 12 1)

r2 2 3 30k

c1 3 0 60p

*****Phase Detector Gain=0.53 x Data Density (Data Density = 1 for clocks) for 5 volt

operation and = 0.35 x Data Density for 3.3 volt operation

e2 4 0 3 0 .35

*****Loop filter

r1 4 5 60k

c2 5 0 10p

rf 5 6 90k

cf 6 7 1.0u

e3 7 0 5 0 –10000

Rev: 30Mar2009