CY24272_11 datasheet(1/16 Pages) CYPRESS

Part #	CY24272

Description	Rambus XDR??Clock Generator with Zero SDA Hold Time

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Manufacturer	CYPRESS [Cypress Semiconductor]

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CY24272

Rambus XDR™ Clock Generator with

Zero SDA Hold Time

Cypress Semiconductor Corporation

•

198 Champion Court

•

San Jose

, CA 95134-1709

•

408-943-2600

Document Number: 001-42414 Rev. *A

Revised February 17, 2011

Rambus‚ XDR™ Clock Generator with Zero SDA Hold Time

Features

■ Meets Rambus Extended Data Rate (XDR™) clocking

requirements

■ 25 ps typical cycle-to-cycle jitter

❐ –135 dBc/Hz typical phase noise at 20 MHz offset

■ 100 or 133 MHz differential clock input

■ 300–667 MHz high speed clock support

■ Quad (open drain) differential output drivers

■ Supports frequency multipliers: 3, 4, 5, 6, 9/2 and 15/4

■ Spread Aware™

■ 2.5 V operation

■ 28-pin TSSOP package

Table 1. Device Comparison

CY24271

CY24272

SDA hold time = 300 ns

(SMBus compliant)

SDA hold time = 0 ns

(I2C compliant)

RRC = 200  typical

(Rambus standard drive)

RRC = 295  minimum

(Reduced output drive)

CLK0

CLK0B

CLK1

CLK1B

CLK2

CLK2B

CLK3

CLK3B

REFCLK,REFCLKB

SCL

SDA

ID0

ID1

EN

RegA

EN

RegB

EN

RegC

EN

RegD

PLL

Bypass

MUX

/BYPASS

EN

Logic Block Diagram

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