Document #: 001-48147 Rev. *C

Page 7 of 15

Switching Characteristics

Over the Operating Range

Parameter[14,15]

Description

45 ns

Unit

Min

Max

Read Cycle

Read cycle time

45

–

ns

Address to data valid

–

45

ns

Data hold from address change

10

–

ns

CE LOW to data valid

–

45

ns

OE LOW to data valid

–

22

ns

OE LOW to Low Z[16]

5

–

ns

OE HIGH to High Z[16, 17]

–

18

ns

CE LOW to Low Z[16]

10

–

ns

CE HIGH to High Z[16, 17]

–

18

ns

CE LOW to power-up

0

–

ns

CE HIGH to ower-down

–

45

ns

BLE/BHE LOW to data valid

–

22

ns

BLE/BHE LOW to Low Z[16]

5

–

ns

BLE/BHE HIGH to High Z[16, 17]

–

18

ns

Write Cycle[18]

Write cycle time

45

–

ns

CE LOW to write end

35

–

ns

Address setup to write end

35

–

ns

Address hold from write end

0

–

ns

Address setup to write start

0

–

ns

WE pulse width

35

–

ns

BLE/BHE LOW to write end

35

–

ns

Data setup to write end

25

–

ns

Data hold from write end

0

–

ns

WE LOW to High Z[16, 17]

–

18

ns

WE HIGH to Low Z[16]

10

–

ns

Notes

14. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0

15. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See application note AN13842 for further clarification

signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.

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