Document #: 38-05577 Rev. *C

Page 7 of 12

Figure 3. Read Cycle No. 2: OE Controlled [19, 20]

Figure 4. Write Cycle No. 1: WE Controlled [21, 23]

50%

50%

DATA VALID

DATA OUT

HIGH IMPEDANCE

IMPEDANCE

OE

CE

HIGH

SUPPLY

CURRENT

ADDRESS

DATA I/O

ADDRESS

CE

WE

OE

NOTE 22

Notes

19. WE is HIGH for read cycle.

20. Address valid prior to or coincident with CE transition LOW.

22. During this period, the I/Os are in output state and input signals should not be applied.

23. If CE goes HIGH simultaneously with WE HIGH, the output remains in high impedance state.

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