Document #: 38-05442 Rev. *H

Page 6 of 14

Figure 3. Data Retention Waveform

Switching Characteristics

Over the operating range

Parameter [14]

Description

45 ns

55 ns[15]

Unit

Min

Max

Min

Max

Read Cycle

Read cycle time

45

–

55

–

ns

Address to data valid

–

45

–

55

ns

Data hold from address change

10

–

10

–

ns

CE LOW to data valid

–45

–

55

ns

OE LOW to data valid

–22

–

25

ns

OE LOW to low Z [16]

5–

5

–

ns

OE HIGH to high Z [16, 17]

–18

–

20

ns

CE LOW to low Z [16]

10

–

10

–

ns

CE HIGH to high Z [16, 17]

–18

–

20

ns

CE LOW to power-up

00

–

ns

CE HIGH to power-down

–45

–

55

ns

Write Cycle[18]

Write cycle time

45

–

55

–

ns

CE LOW to write end

35

–

40

–

ns

Address setup to write end

35

–

40

–

ns

Address hold from write end

0

–

0

–

ns

Address setup to write start

0

–

0

–

ns

WE pulse width

35

–

40

–

ns

Data setup to write end

25

–

25

–

ns

Data hold from write end

0

–

0

–

ns

WE LOW to high Z [16, 17]

–18

–

20

ns

WE HIGH to low Z [16]

10

–

10

–

ns

DATA RETENTION MODE

CE

Notes

14. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels

15. SOIC package is available only in 55 ns speed bin.

terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write.

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