CY62256N

Document Number: 001-06511 Rev. *D

Page 7 of 14

Figure 6. Read Cycle No. 2[17, 18]

Figure 7. Write Cycle No. 1 (WE Controlled)[19, 20, 21]

Figure 8. Write Cycle No. 2 (CE Controlled)[19, 20, 21]

Notes

17. WE is HIGH for Read cycle.

18. Address valid prior to or coincident with CE transition LOW.

19. The internal Write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a Write and either signal can

terminate a Write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the Write.

21. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.

22. During this period, the I/Os are in output state and input signals should not be applied.

50%

50%

DATA VALID

DATA OUT

HIGH IMPEDANCE

IMPEDANCE

ICC

ISB

OE

CE

HIGH

SUPPLY

CURRENT

DATA I/O

ADDRESS

CE

WE

OE

NOTE

22

WE

DATA I/O

ADDRESS

CE

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