CY62256VN

Document Number: 001-06512 Rev. *D

Page 6 of 14

Figure 2. Data Retention Waveform

Switching Characteristics

Over the Operating Range[9]

Parameter

Description

CY62256VN-70

Unit

Min

Max

Read Cycle

Read cycle time

70

–

ns

Address to data valid

–

70

ns

Data hold from address change

10

–

ns

CE LOW to data valid

–

70

ns

OE LOW to data valid

–

35

ns

OE LOW to low Z[10]

5–

ns

OE HIGH to high Z[10, 11]

–25

ns

CE LOW to low Z[10]

10

–

ns

CE HIGH to high Z[10, 11]

–25

ns

CE LOW to power up

0

–

ns

CE HIGH to power down

–

70

ns

Write Cycle[12, 13]

Write cycle time

70

–

ns

CE LOW to write end

60

–

ns

Address setup to write end

60

–

ns

Address hold from write end

0

–

ns

Address setup to write start

0

–

ns

WE pulse width

50

–

ns

Data setup to write end

30

–

ns

Data hold from write end

0

–

ns

WE LOW to high Z[10, 11]

–25

ns

WE HIGH to low Z[10]

10

–

ns

1.8 V

1.8 V

DATA RETENTION MODE

CE

Notes

and 100-pF load capacitance.

12. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate

a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.

[+] Feedback