 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
CYDM256B16-55BVXC Datasheet(PDF) 6 Page - Cypress Semiconductor |
|
||||||||||||||||||||||||||||||
CYDM256B16-55BVXC Datasheet(HTML) 6 Page - Cypress Semiconductor |
|
|
6 / 27 page  CYDM064B16 CYDM128B16 CYDM256B16 Document #: 001-00217 Rev. *H Page 6 of 27 Functional Description The CYDM256B16, CYDM128B16, and CYDM064B16 are low power CMOS 4K, 8K,16K x 16 dual-port static RAMs. Arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. Two ports are provided that permit independent, asynchronous access for reads and writes to any location in memory. The devices can be used as standalone 16-bit dual-port static RAMs or multiple devices can be combined to function as a 32-bit or wider master/slave dual-port static RAM. An M/S pin is provided for implementing 32-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. Application areas include interprocessor or multi- processor designs, communications status buffering, and dual-port video or graphics memory. Each port has independent control pins: Chip Enable (CE), Read or Write Enable (R/W), and Output Enable (OE). Two flags are provided on each port (BUSY and INT). BUSY indicates that the port is trying to access the same location currently being accessed by the other port. The Interrupt flag (INT) permits communication between ports or systems through a mail box. The semaphores are used to pass a flag or token, from one port to the other, to indicate that a shared resource is in use. The semaphore logic consists of eight shared latches. Only one side can control the latch (semaphore) at any time. Control of a semaphore indicates that a shared resource is in use. An automatic power down feature is controlled independently on each port by a Chip Enable (CE) pin. The CYDM256B16, CYDM128B16, CYDM064B16 are available in 100-ball 0.5 mm pitch Ball Grid Array (BGA) packages. Power Supply The core voltage (VCC) can be 1.8V, 2.5V, or 3.0V, as long as it is lower than or equal to the I/O voltage. Each port can operate on independent I/O voltages. This is determined by what is connected to the VDDIOL and VDDIOR pins. The supported I/O standards are 1.8V or 2.5V LVCMOS and 3.0V LVTTL. Write Operation Data must be set up for a duration of tSD before the rising edge of R/W to guarantee a valid write. A write operation is controlled by either the R/W pin (see Figure 5 on page 19) or the CE pin (see Figure 6 on page 19). Required inputs for noncontention operations are summarized in Table 2 on page 8. If a location is being written to by one port and the opposite port attempts to read that location, a port-to-port flowthrough delay must occur before the data is read on the output. Otherwise, the data read is not deterministic. Data is valid on the port tDDD after the data is presented on the other port. Read Operation When reading the device, the user must assert both the OE and CE pins. Data is available tACE after CE or tDOE after OE is asserted. If the user wishes to access a semaphore flag, then the SEM pin must be asserted instead of the CE pin, and OE must also be asserted. Interrupts The upper two memory locations may be used for message passing. The highest memory location (FFF for the CYDM064B16, 1FFF for the CYDM128B16, 3FFF for the CYDM256B16) is the mailbox for the right port and the second-highest memory location (FFE for the CYDM064B16, 1FFE for the CYDM128B16, 3FFE for the CYDM256B16) is the mailbox for the left port. When one port writes to the other port’s mailbox, an interrupt is generated to the owner. The interrupt is reset when the owner reads the contents of the mailbox. The message is user-defined. Each port can read the other port’s mailbox without resetting the interrupt. The active state of the busy signal (to a port) prevents the port from setting the interrupt to the winning port. Also, an active busy to a port prevents that port from reading its own mailbox and, thus, resetting the interrupt to it. If an application does not require message passing, do not connect the interrupt pin to the processor’s interrupt request input pin. On power up, an initialization program must be run and the interrupts for both ports must be read to reset them. The operation of the interrupts and their interaction with Busy are summarized in Table 3 on page 8. Busy The CYDM256B16, CYDM128B16, and CYDM064B16 provide on-chip arbitration to resolve simultaneous memory location access (contention). If both port CEs are asserted and an address match occurs within tPS of each other, the busy logic determines which port has access. If tPS is violated, one port definitely gains permission to the location. However, which port gets this permission cannot be predicted. BUSY is asserted tBLA after an address match or tBLC after CE is taken LOW. Master/Slave An M/S pin is provided to expand the word width by configuring the device as either a master or a slave. The BUSY output of the master is connected to the BUSY input of the slave. This allows the device to interface to a master device with no external components. Writing to slave devices must be delayed until after the BUSY input has settled (tBLC or tBLA). Otherwise, the slave chip may begin a write cycle during a contention situation. When tied HIGH, the M/S pin allows the device to be used as a master and, as a result, the BUSY line is an output. BUSY can then be used to send the arbitration outcome to a slave. [+] Feedback |
Similar Part No. - CYDM256B16-55BVXC |
|
Similar Description - CYDM256B16-55BVXC |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.NET |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
