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CYRF69103-40LFXC Datasheet(PDF) 9 Page - Cypress Semiconductor |
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CYRF69103-40LFXC Datasheet(HTML) 9 Page - Cypress Semiconductor |
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9 / 68 page  CYRF69103 Document #: 001-07611 Rev *F Page 9 of 68 8.6 Interrupts The radio function provides an interrupt (IRQ) output, which is configurable to indicate the occurrence of various different events. The IRQ pin may be programmed to be either active high or active low, and be either a CMOS or open drain output. The radio function features three sets of interrupts: transmit, receive, and system interrupts. These interrupts all share a single pin (IRQ), but can be independently enabled/disabled. In transmit mode, all receive interrupts are automatically disabled, and in receive mode all transmit interrupts are automatically disabled. However, the contents of the enable registers are preserved when switching between transmit and receive modes. If more than one radio interrupt is enabled at any time, it is necessary to read the relevant status register to determine which event caused the IRQ pin to assert. Even when a given interrupt source is disabled, the status of the condition that would otherwise cause an interrupt can be determined by reading the appropriate status register. It is therefore possible to use the devices without making use of the IRQ pin by polling the status register(s) to wait for an event, rather than using the IRQ pin. 8.7 Clocks A 12 MHz crystal (30 ppm or better) is directly connected between XTAL and GND without the need for external capac- itors. A digital clock out function is provided, with selectable output frequencies of 0.75, 1.5, 3, 6, or 12 MHz. This output may be used to clock an external microcontroller (MCU) or ASIC. This output is enabled by default, but may be disabled. The requirements for the crystal to be directly connected to XTAL pin and GND are: ■ Nominal Frequency: 12 MHz ■ Operating Mode: Fundamental Mode ■ Resonance Mode: Parallel Resonant ■ Frequency Initial Stability: ±30 ppm ■ Series Resistance: <60 ohms ■ Load Capacitance: 10 pF ■ Drive Level: l00 μW The MCU function features an internal oscillator. The clock generator provides the 12 MHz and 24 MHz clocks that remain internal to the microcontroller. 8.8 GPIO Interface The MCU function features up to 15 general purpose I/O (GPIO) pins.The I/O pins are grouped into three ports (Port 0 to 2). The pins on Port 0 and Port 1 may each be configured individually while the pins on Port 2 may only be configured as a group. Each GPIO port supports high-impedance inputs, configurable pull up, open drain output, CMOS/TTL inputs, and CMOS output with up to two pins that support programmable drive strength of up to 50 mA sink current. Additionally, each I/O pin can be used to generate a GPIO interrupt to the microcontroller. Each GPIO port has its own GPIO interrupt vector with the exception of GPIO Port 0. GPIO Port 0 has three dedicated pins that have independent interrupt vectors (P0.1, P0.3–P0.4). 8.9 Power On Reset/Low Voltage Detect The power on reset circuit detects logic when power is applied to the device, resets the logic to a known state, and begins executing instructions at Flash address 0x0000. When power falls below a programmable trip voltage, it generates reset or may be configured to generate interrupt. There is a low voltage detect circuit that detects when VCC drops below a programmable trip voltage. It may be configurable to generate an LVD interrupt to inform the processor about the low voltage event. POR and LVD share the same interrupt. There is not a separate interrupt for each. The Watchdog timer can be used to ensure the firmware never gets stalled in an infinite loop. 8.10 Timers The free running 16-bit timer provides two interrupt sources: the programmable interval timer with 1- μs resolution and the 1.024 ms outputs. The timer can be used to measure the duration of an event under firmware control by reading the timer at the start and at the end of an event, then calculating the difference between the two values. 8.11 Power Management The operating voltage of the device is 1.8V to 3.6V DC, which is applied to the VBAT pin. The device can be shut down to a fully static sleep mode by writing to the FRC END = 1 and END STATE = 000 bits in the XACT_CFG_ADR register over the SPI interface. The device enters sleep mode within 35 μs after the last SCK positive edge at the end of this SPI transaction. Alternatively, the device may be configured to automatically enter sleep mode after completing packet transmission or reception. When in sleep mode, the on-chip oscillator is stopped, but the SPI interface remains functional. The device wakes from sleep mode automatically when the device is commanded to enter transmit or receive mode. When resuming from sleep mode, there is a short delay while the oscillator restarts. The device may be configured to assert the IRQ pin when the oscil- lator has stabilized. The output voltage (VREG) of the Power Management Unit (PMU) is configurable to several minimum values between 2.4V and 2.7V. VREG may be used to provide up to 15 mA (average load) to external devices. It is possible to disable the PMU, and to provide an externally regulated DC supply voltage to the device in the range 2.4V to 3.6V. The PMU also provides a regulated 1.8V supply to the logic. The PMU has been designed to provide high boost efficiency (74–85% depending on input voltage, output voltage and load) when using a Schottky diode and power inductor, eliminating the need for an external boost converter in many systems where other components require a boosted voltage. However, reasonable efficiencies (69–82% depending on input voltage, output voltage and load) may be achieved when using low-cost components such as SOT23 diodes and 0805 inductors. The current through the diode must stay within the linear operating range of the diode. For some loads the SOT23 diode is sufficient, but with higher loads it is not and a SS12 diode must be used to stay within this linear range of operation. Along with the diode, the inductor used must not saturate its core. In higher loads, a lower resistance/higher saturation coil like the inductor from Sumida must be used. [+] Feedback |
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