A.C. Characteristics

Ta=25

°C

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

Conditions

System Clock

3V

On-chip RC oscillator

192

256

320

kHz

System Clock

¾ Crystal oscillator

¾

32768

¾

Hz

System Clock

¾ External clock source

¾

256

¾

kHz

LCD Clock

¾ On-chip RC oscillator

¾

¾

Hz

¾ Crystal oscillator

¾

¾

Hz

¾ External clock source

¾

¾

Hz

LCD Common Period

¾ n: Number of COM

¾

¾

s

Serial Data Clock (WR pin)

3V

Duty cycle 50%

4

¾

150

kHz

5V

4

¾

300

kHz

Serial Data Clock (RD pin)

3V

Duty cycle 50%

¾¾

75

kHz

5V

¾¾

150

kHz

Tone Frequency (2kHz)

3V

On-chip RC oscillator

1.5

2.0

2.5

kHz

Tone Frequency (4kHz)

3.0

4.0

5.0

kHz

Serial Interface Reset Pulse

Width (Figure 3)

¾ CS

250

300

¾

ns

WR,RD Input Pulse Width

(Figure 1)

3V

Write mode

3.34

¾

125

ms

Read mode

6.67

¾¾

5V

Write mode

1.67

¾

125

ms

Read mode

3.34

¾¾

Rise/Fall Time Serial Data Clock

Width (Figure 1)

¾¾

¾

120

160

ns

Setup Time for DATA to WR,RD

Clock Width (Figure 2)

¾¾

60

120

¾

ns

Hold Time for DATA to WR,RD

Clock Width (Figure 2)

¾¾

250

300

¾

ns

Setup Time for CS to WR,RD

Clock Width (Figure 3)

¾¾

500

600

¾

ns

Hold Time for CS to WR,RD Clock

Width (Figure 3)

¾¾

50

100

¾

ns

¾

20

¾¾

ms

¾¾

0.05

¾¾

V/ms

Delay Time after Reset (Figure 4)

¾¾

1

¾¾

ms

Note:

1. If the conditions of Power-on Reset timing are not satisfied in power On/Off sequence, the internal

Power-on Reset (POR) circuit will not operate normally.

2. If the VDD drops below the minimum voltage of operating voltage spec. during operating, the conditions

of Power-on Reset timing must be satisfied also. That is, the VDD must drop to 0V and keep at 0V for

20ms (min.) before rising to the normal operating voltage.

HT1621/HT1621G

Rev. 2.90

6

November 9, 2010

PATENTED