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SN65HVD235 Datasheet(PDF) 10 Page - Texas Instruments |
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SN65HVD235 Datasheet(HTML) 10 Page - Texas Instruments |
10 / 158 page SM320F28335-HT www.ti.com SPRS682 – DECEMBER 2010 Digital Signal Controller (DSC) 1 SM320F28335 DSC Resolution 1.1 Features – Up to 6 Event Capture Inputs 12 • High-Performance Static CMOS Technology – Up to 2 Quadrature Encoder Interfaces – Up to 150 MHz for TC = -55°C to 125°C – Up to 8 32-bit/Nine 16-bit Timers and Up to 100 MHZ for TC = 210°C • Three 32-Bit CPU Timers – 1.9-V Core, 3.3-V I/O Design • Serial Port Peripherals • High-Performance 32-Bit CPU – Up to 2 CAN Modules – IEEE-754 Single-Precision Floating-Point – Up to 3 SCI (UART) Modules Unit (FPU) ) – Up to 2 McBSP Modules (Configurable as – 16 x 16 and 32 x 32 MAC Operations SPI) – 16 x 16 Dual MAC – One SPI Module – Harvard Bus Architecture – One Inter-Integrated-Circuit (I2C) Bus – Fast Interrupt Response and Processing • 12-Bit ADC, 16 Channels – Unified Memory Programming Model – 80-ns Conversion Rate – Code-Efficient (in C/C++ and Assembly) – 2 x 8 Channel Input Multiplexer • Six Channel DMA Controller (for ADC, McBSP, – Two Sample-and-Hold ePWM, XINTF, and SARAM) – Single/Simultaneous Conversions • 16-bit or 32-bit External Interface (XINTF) – Internal or External Reference – Over 2M x 16 Address Reach • Up to 88 Individually Programmable, • On-Chip Memory Multiplexed GPIO Pins With Input Filtering – 256K x 16 Flash, 34K x 16 SARAM • JTAG Boundary Scan Support (1) – 1K x 16 OTP ROM • Advanced Emulation Features • Boot ROM (8K x 16) – Analysis and Breakpoint Functions – With Software Boot Modes (via SCI, SPI, – Real-Time Debug via Hardware CAN, I2C, McBSP, XINTF, and Parallel I/O) • Development Support Includes – Standard Math Tables – ANSI C/C++ Compiler/Assembler/Linker • Clock and System Control – Code Composer Studio™ IDE – Dynamic PLL Ratio Changes Supported – DSP/BIOS™ – On-Chip Oscillator – Digital Motor Control and Digital Power – Watchdog Timer Module Software Libraries • GPIO0 to GPIO63 Pins Can Be Connected to • Low-Power Modes and Power Savings One of the Eight External Core Interrupts – IDLE, STANDBY, HALT Modes Supported • Peripheral Interrupt Expansion (PIE) Block That – Disable Individual Peripheral Clocks Supports All 58 Peripheral Interrupts • Package Option • 128-Bit Security Key/Lock – Ceramic Pin Grid Array (GB) – Protects Flash/OTP/RAM Blocks • Temperature Range: – Prevents Firmware Reverse Engineering – –55°C to 210°C • Enhanced Control Peripherals – Up to 18 PWM Outputs (1) IEEE Standard 1149.1-1990 Standard Test Access Port and – Up to 6 HRPWM Outputs With 150 ps MEP Boundary Scan Architecture 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 Code Composer Studio, DSP/BIOS are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Copyright © 2010, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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