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TPS766xx Datasheet(PDF) 8 Page - Texas Instruments |
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TPS766xx Datasheet(HTML) 8 Page - Texas Instruments |
8 / 158 page SM320F28335-HT SPRS682 – DECEMBER 2010 www.ti.com 6-9 Power Management and Supervisory Circuit Solutions ................................................................... 105 6-10 Reset (XRS) Timing Requirements .......................................................................................... 107 6-11 General-Purpose Output Switching Characteristics ........................................................................ 108 6-12 General-Purpose Input Timing Requirements .............................................................................. 109 6-13 IDLE Mode Timing Requirements ........................................................................................... 111 6-14 IDLE Mode Switching Characteristics ....................................................................................... 111 6-15 STANDBY Mode Timing Requirements ..................................................................................... 111 6-16 STANDBY Mode Switching Characteristics ................................................................................ 112 6-17 HALT Mode Timing Requirements ........................................................................................... 113 6-18 HALT Mode Switching Characteristics ...................................................................................... 113 6-19 ePWM Timing Requirements ................................................................................................. 115 6-20 ePWM Switching Characteristics ............................................................................................ 115 6-21 Trip-Zone input Timing Requirements ....................................................................................... 115 6-22 High Resolution PWM Characteristics at SYSCLKOUT = (60 - 120 MHz) .............................................. 116 6-23 Enhanced Capture (eCAP) Timing Requirement .......................................................................... 116 6-24 eCAP Switching Characteristics ............................................................................................. 116 6-25 Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements .................................................. 116 6-26 eQEP Switching Characteristics ............................................................................................. 116 6-27 External ADC Start-of-Conversion Switching Characteristics ............................................................. 117 6-28 External Interrupt Timing Requirements .................................................................................... 117 6-29 External Interrupt Switching Characteristics ................................................................................ 117 6-30 I2C Timing ...................................................................................................................... 118 6-31 SPI Master Mode External Timing (Clock Phase = 0) .................................................................... 119 6-32 SPI Master Mode External Timing (Clock Phase = 1) .................................................................... 121 6-33 SPI Slave Mode External Timing (Clock Phase = 0) ...................................................................... 122 6-34 SPI Slave Mode External Timing (Clock Phase = 1) ...................................................................... 124 6-35 Relationship Between Parameters Configured in XTIMING and Duration of Pulse ................................... 125 6-36 XINTF Clock Configurations ................................................................................................... 128 6-37 External Interface Read Timing Requirements ............................................................................. 129 6-38 External Interface Read Switching Characteristics ......................................................................... 129 6-39 External Interface Write Switching Characteristics ......................................................................... 130 6-40 External Interface Read Switching Characteristics (Ready-on-Read, 1 Wait State) ................................... 132 6-41 External Interface Read Timing Requirements (Ready-on-Read, 1 Wait State) ....................................... 132 6-42 Synchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State) ....................................... 132 6-43 Asynchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State) ....................................... 132 6-44 External Interface Write Switching Characteristics (Ready-on-Write, 1 Wait State) ................................... 135 6-45 Synchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State) ....................................... 135 6-46 Asynchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State) ...................................... 135 6-47 XHOLD/XHOLDA Timing Requirements (XCLKOUT = XTIMCLK) ...................................................... 138 6-48 XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK) ................................................. 139 6-49 ADC Electrical Characteristics (over recommended operating conditions) ............................................ 141 6-50 ADC Power-Up Delays ......................................................................................................... 142 6-51 Typical Current Consumption for Different ADC Configurations (at 25-MHz ADCCLK) .............................. 142 6-52 Sequential Sampling Mode Timing ........................................................................................... 144 6-53 Simultaneous Sampling Mode Timing ....................................................................................... 145 6-54 McBSP Timing Requirements ................................................................................................ 147 6-55 McBSP Switching Characteristics ........................................................................................... 147 6-56 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) ................................ 149 8 List of Tables Copyright © 2010, Texas Instruments Incorporated |
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