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CY2X013LXI156T Datasheet(PDF) 4 Page - Cypress Semiconductor |
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CY2X013LXI156T Datasheet(HTML) 4 Page - Cypress Semiconductor |
4 / 10 page CY2X013 Document Number: 001-10261 Rev. *G Page 4 of 10 Absolute Maximum Conditions Parameter Description Condition Min Max Unit VDD Supply voltage –0.5 4.4 V VIN [1] Input voltage, DC Relative to VSS –0.5 VDD + 0.5 V TS Temperature, storage Non operating –55 135 °C TJ Temperature, junction –40 135 °C ESDHBM Electrostatic discharge (ESD) protection human body model (HBM) JEDEC Std 22-A114-B 2000 – V Θ JA [2] Thermal resistance, junction to ambient 0 m/s airflow 64 °C / W Operating Conditions Parameter Description Min Typ Max Unit VDD 3.3 V supply voltage range 3.0 3.3 3.6 V 2.5 V supply voltage range 2.375 2.5 2.625 V TPU Power-up time for VDD to reach minimum specified voltage (power ramp is monotonic) 0.05 – 500 ms TA Ambient temperature (commercial) 0 – 70 °C Ambient temperature (industrial) –40 – 85 °C Notes 1. The voltage on any input or I/O pin cannot exceed the power pin during power-up. 2. Simulated. The board is derived from the JEDEC multilayer standard. It measures 76 x 114 x 1.6 mm and has 4-layers of copper (2/1/1/2 oz.). The internal layers are 100% copper planes, while the top and bottom layers have 50% metalization. No vias are included in the model. 3. IDD includes ~4 mA of current that is dissipated externally in the output termination resistors. DC Electrical Characteristics Parameter Description Condition Min Typ Max Unit IDD [3] Operating supply current VDD = 3.6 V, OE/PD# = VDD, output terminated – – 125 mA VDD = 2.625 V, OE/PD# = VDD, output terminated – – 120 mA ISB Standby supply current PD# = VSS – – 200 μA VOD LVDS differential output voltage VDD = 3.3 V or 2.5 V, RTERM = 100 Ω between CLK and CLK# 247 – 454 mV ΔV OD Change in VOD between complementary output states VDD = 3.3 V or 2.5 V, RTERM = 100 Ω between CLK and CLK# –– 50 mV VOS LVDS offset output voltage VDD = 3.3 V or 2.5 V, RTERM = 100 Ω between CLK and CLK# 1.125 – 1.375 V ΔV OS Change in VOS between complementary output states VDD = 3.3 V or 2.5 V, RTERM = 100 Ω between CLK and CLK# –– 50 mV IOZ LVDS output leakage current Tri-state output, unterminated, measured on one pin while floating the other pin, PD#/OE = VSS –35 – 35 μA VIH Input high voltage 0.7 × VDD –– V VIL Input low voltage – – 0.3 × VDD V IIH Input high current Input = VDD –– 115 μA IIL Input low current Input = VSS –– 50 μA CIN [3] Input capacitance, OE/PD# pin – 15 – pF [+] Feedback |
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